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Silicon South West, “Testing Times” The Economics of Verification Mike Bartley, TVS

Silicon South West, “Testing Times” The Economics of Verification Mike Bartley, TVS. How can verification deliver value?. What is verification? The economics of verification 100% verification is IMPOSSIBLE How to do verification successfully. The various RTL verification techniques.

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Silicon South West, “Testing Times” The Economics of Verification Mike Bartley, TVS

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  1. Silicon South West, “Testing Times” The Economics of Verification Mike Bartley, TVS

  2. How can verification deliver value? • What is verification? • The economics of verification • 100% verification is IMPOSSIBLE • How to do verification successfully

  3. The various RTL verification techniques Verification Static Dynamic Reviews Code Analysis Formal Simulation Emulation etc Dynamic Formal

  4. Verification consumes the greatest design time Source: EE Times 2006 EDA Users Survey

  5. Poor verification costs money in re-spins Source: Aart de Geus, Chairman and CEO of Synopsys. Based on a survey of 2000 users by Synopsys • “Half of all chip developments require a re-spin, three quarters due to functional bugs”, The 2004/2002 IC/ASIC Functional Verification Study by Collett International Research Reasons for respins Source = Global IC (ASSP/ASIC) Service Management Report 2007, IBS

  6. Economic impact of Verification • Inefficient verification • It is your biggest design task! • Delays to market • Ineffective verification • Your biggest cause for re-spins (and recalls) • Economics of early release • Better, faster verification • Tape-out early with measurable risk

  7. Why is 100% verification impossible? Next State Logic Output Logic X Z Y • Consider an adder • 16 bits→ 8.5 billion tests > 2500 years @ 1 test/second • 2x x 2x x 2y possible input conditions per transition Impossible to prove the absence of bugs

  8. What we want from verification • Demonstrate absence of bugs • Build confidence to ship the product • Defining measurable exit signoff criteria • Demonstrate correctness of prioritised features • Mitigate risk • And stop when cost of further verification outweighs the advantages of increased confidence

  9. Beginning verification earlier brings benefits Verification Effort Effort Design Time Time Verification Effort Verif Effort Design Design Time Time Design Verification • What usually happens? A separate verification team enables this

  10. Team independence in verification RTL coding Interpretation Specification RTL coding Verification Interpretation Specification Interpretation Verification • How hard does somebody try to break their own design? • Verification engineers require different skills and attitudes • Reconvergent paths (Bergeron 2000) Research shows this is the single biggest contributor to higher quality

  11. Good engineering principles delivers benefits • Processes • Stable, clear specifications under change control • Configuration and defect management • Maximise re-use • Well defined signoff targets • People • Verification engineers require different skill sets • Independence • Appropriate tools and methodologies

  12. And what about software! • 20% hardware, 80% software? • Is the Toyota Prius recall the software equivalent of the Intel FPU bug?

  13. Summary • About TVS • About DVClub • “Design IP – help or hindrance to verification”, April 26th • What is verification • Why you should care • Managing it mike@tandvsolns.co.uk • Questions?

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