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The System Bus

The System Bus. Conceptual CPU Block Diagram. Datapath. Control Unit. Buses. Sequencing and Timing Logic. Regs. IR etc. Control Signals. PC etc. PSR. ALU. Status Signals. Bus Interface. Data. Addr. System Bus. Control. CPU. Data. System Bus. Addr. Control. CPU. 32.

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The System Bus

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  1. The System Bus

  2. Conceptual CPU Block Diagram Datapath Control Unit Buses Sequencing and Timing Logic Regs IR etc. Control Signals PC etc. PSR ALU Status Signals Bus Interface Data Addr System Bus Control

  3. CPU Data System Bus Addr Control

  4. CPU 32 Data Bus D0-D31 System Bus 32 Address Bus A0-A31 Control Bus

  5. Single-Bus System: Simplified Block Diagram Input/Output CPU Memory 32 Data Bus System Bus 32 Address Bus Control Bus

  6. Input/Output CPU Memory 32 Data Bus System Bus 32 Address Bus Control Bus Address Obj Code Source Code 00000804 c2002db0 ld [x], %r1 .... 00000db0 fffffffe x: .word -2

  7. Read Cycle Bus Timing (Synchronous Bus) Clock () Time _____MREQ ___RD ___WR ADDR ? Valid ? DATA ? Valid ?

  8. Write Cycle Bus Timing (Synchronous Bus) Clock () Time _____MREQ ___RD ___WR ADDR ? Valid ? DATA ? Valid ?

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