1 / 37

240-334 Computer System Design Lecture 4

Learn the step-by-step design of a processor, including instruction set requirements, components, clocking, testing, and control datapath analysis. Understand performance perspectives and MIPS instruction formats.

eleanorellis
Download Presentation

240-334 Computer System Design Lecture 4

An Image/Link below is provided (as is) to download presentation Download Policy: Content on the Website is provided to you AS IS for your information and personal use and may not be sold / licensed / shared on other websites without getting consent from its author. Content is provided to you AS IS for your information and personal use only. Download presentation by click this link. While downloading, if for some reason you are not able to download a presentation, the publisher may have deleted the file from their server. During download, if you can't get a presentation, the file might be deleted by the publisher.

E N D

Presentation Transcript

  1. 240-334Computer System DesignLecture 4 Wannarat Suntiamorntut 240-334 By Wannarat

  2. Part I : Single Data Path 240-334 By Wannarat

  3. Outline • Design a Processor step by step • Requirement of instruction set • Components and clocking • Testing Datapath • Control Datapath 240-334 By Wannarat

  4. Processor Datapath M E M O R Y Input Control Output Five Component of Computer 240-334 By Wannarat

  5. Performance Perspective • Performance of machine is determined by CPI • Processor Design : clock cycle time clock per instruction • Single cycle processor : adv. : one clock cycle per instruction disadv. : long cycle time 240-334 By Wannarat

  6. Design Processor Step by Step 1. Analyze instruction set ==> Datapath requirement 2. Selection Set of datapath and establish clocking methodology 3. Assembly datapath meeting requirement 4. Analyze implementation of each instruction to determine setting of control 5. Assembly the control logic 240-334 By Wannarat

  7. MIPS Instruction Format 240-334 By Wannarat

  8. Step 1 • ADDU rd, rs, rt SUBU rd, rs, rt • ORI rt, rs, imm16 240-334 By Wannarat

  9. Step 1 • lw rt, rs ,imm16 sw rt, rs, imm16 • beq rs, rt, imm16 240-334 By Wannarat

  10. RTL • All instructions start by fetching Mem[PC] ADDU rd <= rs + rt; PC = PC + 4 SUBU rd <= rs + rt; PC = PC + 4 Ori rt <= rs + zero_ext(imm16);PC = PC + 4 LOAD rt <= mem[rs] + sign_ext(imm16); PC=PC + 4 STORE mem[rs] + sign_ext(imm16)<=rt; PC=PC+4 BEQ if rs = rt then PC=PC+sign_ext(imm16)||00 else PC = PC + 4 240-334 By Wannarat

  11. Step 1 : The requirement from instruction • Memory Data & Instruction • Register (32 x 32) Read rs Read rt Write rt or rd • PC • Extender • Add and sub register or extend immediate • Add 4 or extended immediate to PC 240-334 By Wannarat

  12. Step 2 : Components of datapath • Combination Element • Storage elements Clocking methodology 240-334 By Wannarat

  13. Combination Elements Adder MUX 240-334 By Wannarat

  14. Combination Elements ALU 240-334 By Wannarat

  15. Storage Element : Register • Similar to D-flip/flop • Write enable negated(0) : Data out won’t change asserted(1) : Data out will be data in 240-334 By Wannarat

  16. Register file • Consist of 32 registers • Ra select register to bus A • Rb select register to bus B • Rw select register to be written via bus W 240-334 By Wannarat

  17. Storage : Ideal Memory • One Input • One Output • Memory word is selected by Address, Write enable = 1 then the data will be written • Clock input : is a factor only during write operation • During read operation : behaves on combination logic. 240-334 By Wannarat

  18. Clock Methodology 240-334 By Wannarat

  19. Step 3 : • Register Transfer Requirements --> Datapath Assembly • Instruction Fetch • Read Operands and Execute Operation 240-334 By Wannarat

  20. Step 3 a : Instruction Fetch Unit Update PC : Sequence Code: PC <= PC + 4 Branch and Jump : PC <- something else 240-334 By Wannarat

  21. Step 3b : Add & Sub 240-334 By Wannarat

  22. Register-Register Timing 240-334 By Wannarat

  23. Step 3c :Logical Operations with Immed. 240-334 By Wannarat

  24. Step 3d: Load operations 240-334 By Wannarat

  25. Step 3e : Store Operations 240-334 By Wannarat

  26. Step 3f: Branch instruction beq rs, rt, imme16 • mem[pc] • equal <= rs = rt • if (con eq 0) then PC<=PC+4+(signExt(imm16)x4); else PC <= PC + 4; 240-334 By Wannarat

  27. Datapath for Branch Operations 240-334 By Wannarat

  28. Put it all together 240-334 By Wannarat

  29. Abstract view of critical path 240-334 By Wannarat

  30. Step 4 : Control Path 240-334 By Wannarat

  31. Meaning of control signal • Rs, Rt and Imme16 hardwire to datapath • nPC_sel : 0 => PC • PC<= PC+4, 1 => PC • PC <= PC + 4 + signExt(Imm16) || 00 240-334 By Wannarat

  32. Meaning of control signals ExtOp : Zero, sign MemWr:write memory ALUsrc: 0=>regB, 1=>imme Memtoreg:1=>mem ALUcrt : add, sub, or ReqWr : write dest. Reg. 240-334 By Wannarat

  33. Control Signals 240-334 By Wannarat

  34. Step 5 : Logic for each control signal 240-334 By Wannarat

  35. Example : Load Flow 240-334 By Wannarat

  36. Abstract View of implementation 240-334 By Wannarat

  37. Next on Lecture 5 240-334 By Wannarat

More Related