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241-440 Computer System Design Lecture 2

241-440 Computer System Design Lecture 2. Instruction Set Architecture. What’re the component of ISA?. Machine Instruction Set Instruction format Nature of the fetch through execute. Varies Programming Model. What must an instruction specify?. Which Operation is perform? ADD r1,r2,r3

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241-440 Computer System Design Lecture 2

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  1. 241-440ComputerSystemDesignLecture 2 241-440 by W.S. @ 2009 Instruction Set Architecture

  2. What’re the component of ISA? • Machine Instruction Set • Instruction format • Nature of the fetch through execute 241-440 by W.S. @ 2009

  3. Varies Programming Model 241-440 by W.S. @ 2009

  4. What must an instruction specify? • Which Operation is perform? ADD r1,r2,r3 • Where to find the operands ADD r1,r2,r3 • Place to store the result ADD r1,r2,r3 • Location of next instruction 241-440 by W.S. @ 2009

  5. Basic ISA Class • Accumulator (1 register) 1 address add A; acc <= acc + mem[A] 1 + x address addx A; acc <= acc + mem[A+x] • Stack : 0 address add tos <= tos + next • General Purpose Register 2 address add A, B 3 address add A, B, C 241-440 by W.S. @ 2009

  6. Basic ISA Classes(con’t) • Load/Store load Ra, Rb Ra <= mem[Rb] Store Ra, Rb mem[Rb] <= Ra 241-440 by W.S. @ 2009

  7. Compare number of instruction Code Sequence for C = A + B Stack Accumulator Register Register (reg. - mem) (load/store) Push A Load A Load R1,A Load R1,A Push B Add B Add R1,B Load R2,B Add Store C Store C, R1 Add R3,R1,R2 Pop C Store C,R3 241-440 by W.S. @ 2009

  8. CPU Register Stack Register Arithmetic Register & Address Register 241-440 by W.S. @ 2009

  9. General Purpose Register • 1975 - 1995 all machines use general purpose registers. • Advanced of Registers - faster than memory - easier for compiler to use - hold variables 241-440 by W.S. @ 2009

  10. Summary Instruction Set Class • Data Movement Instructions - Load - Store • Arithmetic and Logic (ALU) Instruction - Add, Sub, Shift … • Branch Instructions - Br, Brz, … 241-440 by W.S. @ 2009

  11. 3-Address Machine and ISA 241-440 by W.S. @ 2009

  12. 2-Address Machine ISA 241-440 by W.S. @ 2009

  13. 1-Address Machine and ISA 241-440 by W.S. @ 2009

  14. 0-Address Machine and ISA 241-440 by W.S. @ 2009

  15. Examples a = (b+c)*d - e 3-address 2-address 1-address stack add a,b,c load a,b load b push b mpy a,a,d add a,c add c push c sub a,a,e mpy a,d mpy d add sub a,e sub e push d store a mpy push e sub pop a 241-440 by W.S. @ 2009

  16. Real Machine • Have mixture of 3, 2, 1 or 0 address instructions • if ALU instructions only use registers for operands and result, machine type is load-store • mix of register-memory and memory-memory 241-440 by W.S. @ 2009

  17. Break 5 Minutes 241-440 by W.S. @ 2009

  18. Addressing Mode 241-440 by W.S. @ 2009

  19. Addressing Mode Addressing Mode Examples Meaning Register Add r4,r3 r4 <= r4 + r3 Immediate Add r4,#3 r4 <= r4 + 3 Displacement Add r4,100(r1) r4 <= r4 + mem[100+r1] indirect(r) Add r4,(r1) r4 <= r4 + mem[r1] index+base Add r3,(r1+r2) r3 <= r3 + mem[r1+r2] Direct Add r1,(1001) r1 <= r1 + mem[1001] indirect(m) Add r1,@(r3) r1 <= r1 + mem[mem[r3]] auto-incre Add r1,(r2)+ r1 <= r1+mem[r2];r2=r2+d auto-decre Add r1,-(r2) r2 <=r2-d,r1<=r1+mem[r2] scaledAdd r1,100(r2)[r3] r1 <=r1+mem[100+r2+r3*d] 241-440 by W.S. @ 2009

  20. MIPS Registers • 31 x 32-bit GPR (R0 = 0) • 32 x 32-bit FP register • PC • lo hi-multiplier output register 241-440 by W.S. @ 2009 R0 R1 R31 PC lo hi

  21. Memory Addressing • Since 1980, Most machine uses address to level of 8-bits (byte) • How do byte address map onto words? • Can a word be placed on any byte boundary? 241-440 by W.S. @ 2009

  22. Endianess and Alignment • Big Endian : 68k, SPARC, MIPS, HP PA • Little Endian : 80x86,DEC(Vax, Alpha) 241-440 by W.S. @ 2009

  23. Generic of Instruction format width Variable : Fixed: Hybrid : ... 241-440 by W.S. @ 2009

  24. Summary ISA • Variable length instructions, if code size is very important. • Fixed length instructions, if performance is most important. • Embedded Machine (ARM, MIPS) have optional mode to execute 16-bit wide. (decide performance or density) 241-440 by W.S. @ 2009

  25. To be Continuous 241-440 by W.S. @ 2009

  26. Part II : Lecture 2 241-440 by W.S. @ 2009

  27. MIPS ISA Target • Embedded System • used by NEC, Nintendo, Silicon Graphics, Sony 241-440 by W.S. @ 2009

  28. MIPS ISA 241-440 by W.S. @ 2009

  29. MIPS Addressing Modes • All instructions have 32-bit wide. 241-440 by W.S. @ 2009

  30. MIPS Arithmetic Instruction Instruction Example Meaning 1.add add $1,$2,$3 $1 = $2 + $3 2.subtract sub $1,$2,$3 ------------------ 3.add imme addi $1,$2,100 ------------------ 4.add unsign addu $1,$2,$3 ------------------ 5. subu $1,$2,$3 ------------------ 6. addiu $1,$2,100 ----------------- 7.multiply mult $2,$3 Hi,Lo = $2x$3 8. multu $2,$3 ------------------ 241-440 by W.S. @ 2009

  31. MIPS Arithmetic Instruction Instruction Example Meaning 9.divide div $2,$3 Lo=$2/$3, Hi=$2mod$3, 10. Divu $2,$3 11.mov mfhi $1 12. mflo $1 241-440 by W.S. @ 2009

  32. MIPS Logical Instruction Instruction Example Meaning 13.AND and 14.OR or 15.XOR xor 16.NOR nor 17. andi 18. ori 19. xori 20.shift left logical sll $1,$2,10 21. Srl $1,$2,10 241-440 by W.S. @ 2009

  33. MIPS Logical Instruction Instruction Example Meaning 22.shift right arithm sra $,$2,10 (sign extend) 23. sllv 24. srlv 25. srav 241-440 by W.S. @ 2009

  34. MIPS data transfer instructions 26. sw 500(r4),r3 Store word 27. sh 502(r4),r3 store half word 28. sb 41(r4,r3 store byte 29. lw r1,30(r2) load word 30. Lh r1,40(r2) load half word 31. Lb r1,40(r2) load byte 32 lui r1,40 load upper immediate (16 bits shifted left by 16) 241-440 by W.S. @ 2009

  35. Testing Condition • Condition Code add r1,r2,r3 bz label • Condition Register cmp r1,r2,r3 bgt r1,label • Compare and Branch bgt r1,r2,label 241-440 by W.S. @ 2009

  36. MIPS Compare and Branch • Compare and Branch BEQ rs,rt,offset BNE rs,rt,offset • compare to zero and Branch BLEZ rs, offset BGTZ rs, offset BLT < BGEZ >= BLTZAL if R[rs] < 0 then branch and link(to R31) BGEZAL >= 241-440 by W.S. @ 2009

  37. MIPS Jump, Branch Compare 241-440 by W.S. @ 2009

  38. Software conventions for Register 241-440 by W.S. @ 2009

  39. Note for MIPS Instruction Set • R0 always = “0” (even if u try to write) • Branch/jump and link PC+4 ->R31 • Imme arith and logical are extended - logical imme op are zero extend to 32 bits - arith imme op are sign extend to 32 bits • data loaded by lb, lh extended - lbu, lhu are zero extended - lb, lh are sign extedned • Overflow occur in ADD, SUB, ADDI • Don’t occur in ADDU, SUBU, ADDIU, AND, OR, XOR, NOR, SHIFT, MULT, MULTU, DIV, DIVU 241-440 by W.S. @ 2009

  40. MIPS arithmetic • Instruction has 3 operands • Operand order is fixed Pascal Code : a := b + c; MIPS Code : add $s0, $s1, $s2 241-440 by W.S. @ 2009

  41. MIPS Arithmetic Pascal Code : a := b + c + d; e := f - a; MIPS Code : add $t0, $s1, $s2 add $s0, $t0, $s3 sub $s4, $s5, $s0 241-440 by W.S. @ 2009

  42. Register & Memory • Registers were used in Arithmetic Instructions - 32 registers 241-440 by W.S. @ 2009

  43. 1 8 bits of Data 2 8 bits of Data 3 8 bits of Data 4 8 bits of Data 5 8 bits of Data 6 8 bits of Data 7 8 bits of Data Memory Organization • Memory is an index into the array • Byte Addressing = points to a byte of memory 241-440 by W.S. @ 2009

  44. 0 32 bits of Data 4 32 bits of Data 8 32 bits of Data 12 32 bits of Data 16 32 bits of Data 20 32 bits of Data 24 32 bits of Data Memory Organization • For MIPS, a word is 32-bit or 4 bytes • 232 bytes with byte addresses from 0 to 232-1 • 230 words with byte address from 0, 4, 6, …,232-4 241-440 by W.S. @ 2009

  45. MIPS Load/Store Instruction Code : A[8] = h + A[8]; A[8] ==> 8 x 4 = 32 (word alignment) MIPS Code : lw $t0, 32($s3); add $t0,$s2,$t0; sw $t0, 32($s3); Arithmetic Operand is Register, not Memory!! 241-440 by W.S. @ 2009

  46. Example : • Swap (int v[], int k); { Int temp; temp = v[k]; v[k] = v[k+1]; swap: v[k+1]=temp; lw $15, 0[$2] } lw $16, 4[$2] sw $16, 0[$2] sw $15, 4[$2] jr $31 241-440 by W.S. @ 2009

  47. Meaning add $2, $4, $2 $2 = $4 + $2; lw $16, 0[$2] $16 = Memory[0 + $2] sw $15, 4[$2] Memory[4+$2] = $15 241-440 by W.S. @ 2009

  48. Machine Language • Instructions, like register & words of data are 32 bits long. - add $t0, $s1, $s2 - register : $t0 = 9, $s1 = 17, $s2 = 18 • Instruction Format 241-440 by W.S. @ 2009

  49. Machine Language • I-type for Data transfer instruction • Example : lw $t0, 32($s2) 241-440 by W.S. @ 2009

  50. Control • Decision Making instructions • MIPS conditional branch instructions: - bne $t0, $t1, label - beq $t0, $t1, label • Example : if (i=j) h= i +j; bne $s0, $s1, Label add $s3, $s0, $s1 Label : ... 241-440 by W.S. @ 2009

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