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CMOS Fabrication

CMOS Fabrication. EMT 251. Objectives. To discussed the fundamentals of CMOS fabrication steps. To examined the major steps of the process flow. To overview the cross section view of a circuit. Chip making Process. CMOS. PMOS. NMOS. Introduction. MOSFET. MOSFET. Gate. Drain. Source.

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CMOS Fabrication

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  1. CMOS Fabrication EMT 251

  2. Objectives • To discussed the fundamentals of CMOS fabrication steps. • To examined the major steps of the process flow. • To overview the cross section view of a circuit

  3. Chip making Process

  4. CMOS PMOS NMOS Introduction MOSFET

  5. MOSFET Gate Drain Source • Metal Oxide Semiconductor Field Effect Transistor • Source (Arsenic, Phosphorous, Boron) • Drain (Arsenic, Phosphorous, Boron) • Gate (Aluminum, Polysilicon)

  6. P-type substrate NMOS • N-type dopant for Source & Drain • Inversion layer is formed to conduct electricity

  7. P-type substrate NMOS • N-type dopant for Source & Drain • Inversion layer is formed to conduct electricity

  8. N-type substrate PMOS • P-type dopant for Source & Drain • Inversion layer is formed to conduct electricity

  9. N-type substrate PMOS • P-type dopant for Source & Drain • Inversion layer is formed to conduct electricity

  10. A combination of both NMOS & PMOS technology CMOS • Most basic example: inverter

  11. WELL FORMATION ISOLATION FORMATION TRANSISTOR MAKING INTERCONNECTION PASSIVATION PROCESS FLOW

  12. CMOS FABRICATION PROCESSwell formation • Start with clean p-type substrate (p-type wafer)

  13. CMOS FABRICATION PROCESSwell formation • Grow epitaxy layer (made from SiO2) as mask layer for well formation

  14. CMOS FABRICATION PROCESSwell formation • By *photolithography and etching process, well opening are made *photolithography and etch processes are shown in next slides Well will be formed here

  15. Photolithography (CED) photoresist Si02 • Photoresist coating (C) • Masking and exposure under UV light(E) • Resist dissolved after developed (D) • Pre-shape the well pattern at resist layer P-substrate UV light mask Opaque area P-substrate Transparent area

  16. etching • Removing the unwanted pattern by wet etching • Resist clean • Desired pattern formed P-substrate P-substrate

  17. CMOS FABRICATION PROCESSwell formation • Ion bombardment by ion implantation • SiO2 as mask, uncovered area will exposed to dophant ion Phosphorus ion

  18. CMOS FABRICATION PROCESSisolation formation • Increase SiO2 thickness by oxidation at high temperature • Oxide will electrically isolates nmos and pmos devices Thick oxide

  19. CMOS FABRICATION PROCESStransistor making • By photolithography and etching process, pmos and nmos areas are defined pmos will be formed here nmos will be formed here LOCOS (isolation structure)

  20. CMOS FABRICATION PROCESStransistor making • Grow very thin gate oxide at elevated temperature in very short time Gate oxide

  21. CMOS FABRICATION PROCESStransistor making • Deposit polisilicon layer polisilicon

  22. CMOS FABRICATION PROCESStransistor making • Photolithography (photo) and etching to form gate pattern gate

  23. CMOS FABRICATION PROCESStransistor making Arsenic ion • Photo process to define the nmos’s active (source and drain) area and VDD contact • Ion implantation with Arsenic ion for n+ dophant. • Photoresist and polisilicon gate act as mask photoresist

  24. CMOS FABRICATION PROCESStransistor making • Nmos’s Source and drain with VDD contact formation • Resist removal VDD contact source drain

  25. CMOS FABRICATION PROCESStransistor making • Photo process to define the GND contact and pmos’s active area (source and drain) • Ion implantation with boron ionto have p+ dophant • Photoresist and gate act as mask Boron ion photoresist

  26. CMOS FABRICATION PROCESStransistor making • Pmos’s source and drain formation with GND contact • Resist removal GND contact Pmos’s drain Pmos’ source

  27. CMOS FABRICATION PROCESSinterconnection • Deposit SiO2 layer through out wafer surface SiO2

  28. CMOS FABRICATION PROCESSinterconnection • Photo and etching process to make contact contact

  29. CMOS FABRICATION PROCESSinterconnection • Metal 1 deposition throughout wafer surface Metal 1

  30. CMOS FABRICATION PROCESSinterconnection • Photo and etching processes to pattern interconnection

  31. Mask Layout

  32. Mask Layout

  33. Mask Layout

  34. Mask Layout

  35. A’ A N-well Metal 1 oxide p+ n+ n+ p+ p-substrate n+

  36. B B’ Assignment

  37. GLOSSARY • Photolithography (photo) • Process of transferring pattern on mask to photoresist layer on wafer surface (pre-pattern the chip) • Etching • Process of permanently removed the unwanted part of design on wafer surface to get the desired pattern • Diffusion • Process of introducing dophant layer by movement of dophant atoms from high concentration to low concentration area at high temperature • Ion implantation • Process of introducing dophant layer by bombardment of high energy dophant ion in high electric field chamber • Oxidation • Process of growing thick or thin SiO2 layer depend on oxide application • CMP • Process to physically grind flat to have a planar surface for better exposure at photo process.

  38. THE END

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