Interconnect and Packaging

1. Interconnect and Packaging Chung-Kuan Cheng UC San Diego Lecture 7: Distortionless Communication

2. Distortionless Communication • Introduction of distortionless interconnect • Architecture of Surfliner • Implementation • Applications

3. I. Interconnect Models • Voltage drops through serial resistance and inductance • Current reduces through shunt capacitance • Resistance increases due to skin effect • Shunt conductance is caused by loss tangent

4. I. Interconnect Models • Telegrapher’s equation: • Propagation Constant: • Wave Propagation: • Characteristic Impedance

5. I. Introduction of Distortionless Interconnect • Distortion: Transfer function H(S) != const. Digital signal contains multiple freqs. Intersymbol interference • Usage of limited frequency range • Pre-emphasis at transmitter HT(S) Equalization at receiver HR(S) HT(S)H(S)HR(S) ~=const. • Surfliner: HSurfliner(S) = const.

6. II. Distortion: Frequency Ranges and Equalization Z-1 Z-1 c b a Input Signal Frequency Range Trimming • Encoding (8B/10B) • Data Scrambling • Aliasing Equalization HE=a+bZ-1+cZ-2

7. II. Equalization Courtesy of Ed Lee

8. III. Distortionless Interconnect • On-chip Global Interconnect trend • Concerns: Speed, Power, Cost, Reliability

9. III. Introduction of distortionless interconnect • Speed-of-the-light on-chip communication • < 1/5 Delay of Traditional Wires • Low Power Consumption • < 1/5 Power Consumption • Robust against process variations • Short Latency • Insensitive to Feature Size

10. IV. Architecture of Surfliner Differential Lossy Transmission Line Surfliner • Add shunt conductance to compensate current loss R/G = L/C • Flat from DC Mode to Giga Hz • Telegraph Cable: O. Heaviside in 1887. • Current loss through shunt capacitance • Frequency dependent phase velocity (speed) and attenuation

11. IV. Architecture of Surfliner • Set R/G=C/L • Frequency Independentspeed and attenuation: • Characteristic impedance: (pure resistive) • Phase Velocity (Speed of light in the media) • Attenuation:

12. IV. Architecture: Signal Response

13. IV. Architecture: Eye Diagram • Injected 1.0V voltage falls to 365mv over a 2cm wire 120 stage, 2.1ps jitter

14. IV. Architecture: Speed, Power, Variations • Speed of Light: 5ps/mm or 50ps/cm • Power: 10mW at >GHz • Conductance variation = 10%, f=10MHz~10GHz • Phase velocity variation < 1% • Attenuation variation < 5%

15. V. Implementation • Add shunt conductance between differential wires • Resistors realized by serpentine unsilicided poly, diffusion resistors, or high resistive metal

16. V. Implementation • Configuration of wires • Characteristic Impedance (at 10GHz) : 39.915 Ohm • Inductance: 0.22nH/mm Capacitance: 141fF/mm • Attenuation: 253mv magnitude at receiver’s end (assuming 1V at sender’s end) • Using Microstrip (free space above the wires): impedance can be improved to 52.8Ohm

17. V. Simulation • Agilent ADS Momentum extract 4-port S-parameters • HSpice: Transient analysis • Assume 1023 bit pseudo random bit sequence (PRBS) • 15GHz clock • 10% of clock period transition slope for each rising and falling edge

18. V. Simulation Results 120 Stages 4 Stages

19. V. Simulation Results Jitter and silicon area usage Power w/ different width and separation

20. VI. Applications of Surfliner 1.Clock distributions 2. Data communications: Buses Between CPUs, DSPs, Memory Banks

21. VI. Application of Surfliner 3. High Performance Low Power Wafer Packaging