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Initial Global Routing in Floorplanning by EQ -Sequence. Hua-An ZHAO , Chen LIU and Qingsheng HU ISIE 2008(International Symposium on Industrial Electronics ). Abstract. Floorplanning provides the first estimates of performance and cost including placement and routing.
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Initial Global Routing in Floorplanningby EQ-Sequence Hua-An ZHAO , Chen LIU and Qingsheng HU ISIE 2008(International Symposium on Industrial Electronics )
Abstract • Floorplanning provides the first estimates of performance and cost including placement and routing. • This paper represent the floorplan by an EQ-sequence. • The algorithm is based on computing the Steiner trees • The aim is to get a minimum chip area and the shortest total length of wires where the longest (critical) wire in every net is reduced to a minimum.
Abe Order and Other Definitions(1/4) • The boundaries of the chip are called walls. • The top (left, right and bottom) of the boundary is called top (left, right and bottom)-wall, denoted by WT(WL, WRand WB). • The step of Abe order: • consider the left-top room and label it “1” • focus on the right-bottom corner of the room. If the segment which ends here is vertical (horizontal), the top room (left-most room) of the rooms on the other side is labelled “2”. • Continue the process with respect to the current room to label the next room until the right-bottom room is labelled. • It can be seen that the Abe order is an order visiting every room in a floorplan.
Abe Order and Other Definitions(3/4) • The segment that ends at the T-junction is called the prime seg of i, denoted by pi. • The associated room set Ai is a set of all rooms that abut on the prime seg pi and on the opposite side of room i. • The inside room set Ii is a set of all rooms adjoining pi on the same side of i. • Note that the rooms in Ai and Ii are arranged by increasing order. • The adjacent number Si of room i is the number of the rooms which are below (right-of) i and abut i when pi is vertical (horizontal). If the below (right-of) i is wall, Si=0.
Abe Order and Other Definitions(4/4) • EX: • A1={2}, A2={3, 4}, A3={4, 5, 8}, A4={5}, A5={6, 7}, A6={7}, A7={8} and AL={1, 3}, AT={1, 2, 6}. • The adjacent number are S1=1, S2=1, S3=0, S4=2, S5=1, S6=0 and S7=0. • The inside room sets are I1={1}, I2={1, 2}, I3={3}, I4={4}, I5={2, 4, 5} , I6={6}, I7={5, 7}.
Q-sequence and EQ-sequence(1/3) • Q = Q(WR)Q(WB)Q(1)Q(2) ···Q(n). • Q(i) be the sequence of symbols R (if the prime seg of r(i) is vertical) or B (if the prime seg is horizontal) with subscripts of the associated rooms of r(i) in the decreasing order of Abe ordering. • EX: • WLR3R1 WTB6B2B1 1R2 2B4B3 3R8R5R4 4B5 5R7R6 6B7 7B8 8 • A1={2}, A2={3, 4}, A3={4, 5, 8}, A4={5}, A5={6, 7}, A6={7}, A7={8} and AL={1, 3}, AT={1, 2, 6}.
Q-sequence and EQ-sequence(2/3) • WLN0R3R1 WTN0B6B2B1 1N1R2 2N1B4B3 3N0R8R5R4 4N2B5 5N1R7R6 6N0B7 7N0B8 8 • WLN0R3R1 WTN0B6B2B1 1N2R2 2N1B4B3 3N0R8R5R4 4N2B5 5N1R7R6 6N0B7 7N0B8 8
Q-sequence and EQ-sequence(3/3) • It is evident that all NSi are deleted from the EQ-sequence, it is reduced to the Q-sequence. • In placement, however, the NSi is not necessary, that is, EQ-sequence and Q-sequence have the same performances in placement processing.
PLACEMENT BY EQ-SEQUENCE • moving by one of three operations randomly: (1)changing the EQ-sequence, (2) changing the assignment table where the corresponding relations of rooms and modules are indicated (3) changing the height and width of some modules (rotate the modules). • The optimizing method is either the simulated annealing (S.A) or genetic algorithm (G.A).
Channel Generating(1/2) • divide each prime seg pi by whose associated room set Ai and inside room set Ii, these become some routing channels to realize the channel generations. • number of channels corresponding to pi is |Ai | + |Ii |-1. • for channel utilizations, should keep all channels about equally full to minimize wasted area, to rip-up wires or to reroute so that the critical wire in every net becomes minimal to improve the global routing qualites.
Channel Generating(2/2) • EX: • A1 ={2, 3}, A2 ={3},A3={4, 5}, A4={5, 7}, A5={6}, A6={7}. • I1={1}, I2={2}, I3={2, 3}, I4={4}, I5={1, 3, 5} , I6={5, 6}.
Global Routing • First decompose multi-pin nets into sets of point to point connections, and then route each connection. • In this work use the Steiner tree heuristic. This heuristic obtains good quality trees (close to optimal on random problems), and • also has low complexity;the implementation is O(n2). • Each wire is routed using a maze router; • Have to implemented Dijkstra’s algorithm, taking care to ensure that the implementation is efficient. • Finally, can obtain a minimized net length, which is important for the approach to be used in practice.
CONCLUDING • The future work involves applying different multi-objective optimization methods to detailed routing and in particular considering such as power dissipation and performance and so on.