Digital Systems Design 2

1. Digital Systems Design 2 VHDL & State Machines

2. Finite State Machines • The most general model of sequential circuit has inputs, outputs and internal states. • Two types of models are distinguished based on the way the output is generated: • Mealy model and • Moore model • In the Mealy model the output is a function of both the present state and the input. • In the Moore model the output is a function of present state only. Veton Këpuska

3. Mealy Machine • Next State = F(current state, input) • Ouput = G(current state, input) Inputs Next State Combinational Logic F Output Logic G State Memory Clock input Outputs Clock Signal Veton Këpuska

4. Moore Machine • Next State = F(current state, input) • Ouput = G(current state) Inputs Next State Combinational Logic F Output Logic G State Memory Clock input Outputs Clock Signal Veton Këpuska

5. Traffic Signal Example • Each traffic light has to lights: • Red • Green • Major road normally has the green light. • Minor road has red light. • If a car is detected on the minor road: • The signals change to RED for major road and GREEN for minor road. • The timer is started. • Once timer completes a TIMED signal is asserted which cases the lights to change back to their default state. Major Road Minor Road Sensor Veton Këpuska

6. State Machine Graph of Traffic Signal Controller not CAR CAR/START_TIMER MAJOR=G MINOR=R MAJOR=R MINOR=G TIMED not TIMED Veton Këpuska

7. State Name Output Signals State Machine Charts • State Machine (SM) Charts Resemble flow Charts: • SM Charts represent physical hardware • Basic Components: • State Box • Decision Box • Conditional Output Box Optional State Assignment 1011 A 0 X=1 Y J Z=1 1 Conditional Output box Decision box State box Veton Këpuska

8. SM Chart of Traffic Example G MAJOR=GRN MINOR=RED 0 CAR 1 clock cycle 1 START_TIMER R MAJOR=RED MINOR=GRN 1 0 TIMED Veton Këpuska

9. Topics from Logic Design • Synthesis from SM Charts • State Assignment • State Minimization Veton Këpuska

10. SM in VHDL • State machines can be described using concurrent VHDL constructs. • It is far easier using sequential VHDL. • Process modeling combinational block must include all the inputs in its sensitivity list. • Since a state machine changes its sate at clock edge the sensitivity list of the process modeling state transitions must include a clock input. • State of the system must be held in an internal variable. Veton Këpuska

11. SM in VHDL • State can be represented by an enumerated type: • typestate_typeis (state_name1, state_name2, …, state_nameN); • variablestate: state_type; • Because abstract names are used for state names it is not necessary to perform state assignment. Veton Këpuska

12. VHDL SM traffic examples libraryieee; useieee.std_logic_1164.all; entity traffic is port ( clock, timed, car: instd_ulogic; start_timer, major_green, minor_green: outstd_ulogic); end entitytraffic; architectureasm1oftrafficis begin process (clock, timed, car) is typestate_typeis (G, R); variable state: state_type; being start_timer <= ‘0’; case state is when G => major_green <= ‘1’; minor_green <= ‘0’; if (car = ‘1’) then start_timer <= ‘1’; if (rising_edge(clock)) then state := R; end if; end if; when R => major_green <= ‘0’; minor_green <= ‘1’; if (car = ‘1’) then start_timer <= ‘1’; if (timed = ‘1’ and rising_edge(clock)) then state := G; end if; end if; end case; end process; end architecture asm1; Veton Këpuska

13. VHDL SM traffic examples (cont) • Previous implementation may have problems with many synthesis tools. • It is more usual to have one edge detection statement at the beginning of a process as shown in the next slide: Veton Këpuska

14. VHDL SM traffic examples (cont) process (clock, timed, car) is typestate_typeis (G, R); variable state: state_type; being start_timer <= ‘0’; if (rising_edge(clock)) then case state is when G => major_green <= ‘1’; minor_green <= ‘0’; if (car = ‘1’) then start_timer <= ‘1’; state := R; end if; when R => major_green <= ‘0’; minor_green <= ‘1’; if (timed = ‘1’) then start_timer <= ‘1’; state := G; end if; end case; end process; Veton Këpuska

15. VHDL SM traffic examples (cont) • Most synthesis tools expect there to be one edge-sensitive statement in a process. • It is not possible to correctly model state machines with Mealy outputs using a single VHDL process. • Thus a common modeling style for state machines therefore uses two processes. • One process is used to models state registers, and • The second process models next state and output logic. • Those two processes correspond to the general state machine depicted in the next slide. Veton Këpuska

16. Inputs Outputs Combinational Model PresentState NextState State Registers General SM Model • General Sequential System Veton Këpuska

17. VHDL SM traffic example: two-process model architectureasm2oftrafficis typestate_typeis (G, R); variable present_state, next_state: state_type; begin seq: process (clock) is begin if (rising_edge(clock)) then present_state <= next_state; end if; end process seq; com: process (car, timed, present_state) is begin start_timer <= ‘0’; case preset_state is when G => major_green <= ‘1’; minor_green <= ‘0’; if (car = ‘1’) then start_timer <= ‘1’; next_state := R; else next_state := G; end if; when R => major_green <= ‘0’; minor_green <= ‘1’; if (timed = ‘1’) then next_state := G; else next_state := R; end if; end case; end process com; end architecture asm2; Veton Këpuska

18. ns: process (car, timed, present_state) is begin case preset_state is when G => if (car = ‘1’) then next_state := R; else next_state := G; end if; when R => if (timed = ‘1’) then next_state := G; else next_state := R; end if; end case; end process ns; outp: process (car, timed, present_state) is begin start_timer <= ‘0’; if (preset_state = G) then major_green <= ‘1’; minor_green <= ‘0’; if (car = ‘1’) then start_timer <= ‘1’; end if; else major_green <= ‘0’; minor_green <= ‘1’; end if; end process outp; VHDL SM traffic example: three-process model Veton Këpuska

19. outp: process (car, timed, present_state) is begin case preset_state is when G => major_green <= ‘1’; minor_green <= ‘0’; if (car = ‘1’) then start_timer <= ‘1’; end if; when R => major_green <= ‘0’; minor_green <= ‘1’; end case; end process outp; outp: process (car, timed, present_state) is begin start_timer <= ‘1’ when (preset_state = G) and (car = ‘1’) else ‘0’; major_green <= ‘1’; when (preset_state = G) else ‘0’; minor_green <= ‘1’; when (preset_state = R) else ‘0’; end process outp; Alternative VHDL realizations for outp process Veton Këpuska