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Digital Systems Design 2

Digital Systems Design 2. Basic Elements of Combinational Logic Designs Chapter 5 of “Digital Design Principles and Practices”, John F. Wakerly, Prentice Hall, 2001, Third Edition. Decoders. General decoder structure Typically n inputs, 2 n outputs 2-to-4, 3-to-8, 4-to-16, etc.

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Digital Systems Design 2

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  1. Digital Systems Design 2 Basic Elements of Combinational Logic Designs Chapter 5 of “Digital Design Principles and Practices”, John F. Wakerly, Prentice Hall, 2001, Third Edition

  2. Decoders • General decoder structure • Typically n inputs, 2n outputs • 2-to-4, 3-to-8, 4-to-16, etc. Veton Këpuska

  3. Decoder applications • Microprocessor memory systems • selecting different banks of memory • Microprocessor input/output systems • selecting different devices • Microprocessor instruction decoding • enabling different functional units • Memory chips • enabling different rows of memory depending on address • Lots of other applications Veton Këpuska

  4. Note “x” (don’t care) notation. Binary 2-to-4 decoder Veton Këpuska

  5. 2-to-4-decoder logic diagram Veton Këpuska

  6. VHDL Structural program for 2-to-4-decoder library IEEE; use IEEE.std_logic_1164.all; entity v2to4dec is port ( I0,I1,EN: in STD_LOGIC; Y0,Y1,Y2,Y3: out STD_LOGIC ); end v2to4dec; architecture v2to4dec_s of v2to4dec is signal NOTI0, NOTI1: STD_LOGIC; component inv port(I: in STD_LOGIC; O: out STD_LOGIC); end component; component and3 port(I0,I1,I2: in STD_LOGIC; 0: out STD_LOGIC); end component; begin U1: inv port map (I0,NOTI0); U2: inv port map (I1,NOTI1); U3: and3 port map (NOTI0,NOTI1,EN,Y0); U4: and3 port map ( I0,NOTI1,EN,Y1); U5: and3 port map (NOTI0, I1,EN,Y2); U6: and3 port map ( I0, I1,EN,Y3); end v2to4dec_s; Veton Këpuska

  7. MSI 2-to-4 decoder • Input buffering (less load) • NAND gates (faster) Veton Këpuska

  8. Decoder Symbol Veton Këpuska

  9. Complete 74x139 Decoder Veton Këpuska

  10. 3-to-8 decoder Veton Këpuska

  11. 74x138 3-to-8-decoder symbol Veton Këpuska

  12. Dataflow-style VHDL program for 3-to-8-decoder library IEEE; use IEEE.std_logic_1164.all; entity v74x138 is port(G1,G2A_L,G2B_L: in STD_LOGIC; -- enable inputs A: in STD_LOGIC_VECTOR(2 downto 0); -- select inputs Y_L: out STD_LOGIC_VECTOR(0 to 7)); -- decoded outputs end v74x138; architecture v74x138_a of v74x138 is signal Y_L_i: STD_LOGIC_VECTOR(0 to 7); begin with A select Y_L_i <= “01111111” when “000”, “10111111” when “001”, “11011111” when “010”, “11101111” when “011”, “11110111” when “100”, “11111011” when “101”, “11111101” when “110”, “11111110” when “111”, “11111111” when others; Y_L <= Y_L_i when (G1 and not G2A_L and not G2B_L) = ‘1’ else “11111111”; end v74x138_a; Veton Këpuska

  13. VHDL architecture with maintainable approach to active-level handling: 3-to-8-decoder architecture v74x138_b of v74x138 is signal G2A, G2B: STD_LOGIC; -- active high version of inputs signal Y: STD_LOGIC_VECTOR(0 to 7); -- active high version of outputs signal Y_s: STD_LOGIC_VECTOR(0 to 7); -- internal signal begin G2A <= not G2A_L; -- convert inputs G2B <= not G2B_L; -- convert inputs Y <= not Y_L; -- convert outputs with A select Y_s <= “10000000” when “000”, “01000000” when “001”, “00100000” when “010”, “00010000” when “011”, “00001000” when “100”, “00000100” when “101”, “00000010” when “110”, “00000001” when “111”, “00000000” when others; Y_L <= Y_s when (G1 and G2A and G2B) = ‘1’ else “00000000”; end v74x138_b; Veton Këpuska

  14. Hierarchical definition of 74x138-like decoder with active-level handling. architecture v74x138_c of v74x138 is signal G2A, G2B: STD_LOGIC; -- active high version of inputs signal Y: STD_LOGIC_VECTOR(0 to 7); -- active high version of outputs component v3to8dec port (G1,G2,G3: in STD_LOGIC; A: in STD_LOGIC_VECTOR (2 donwto 0); Y: out STD_LOGIC_VECTOR (0 to 7) ); begin G2A <= not G2A_L; -- convert inputs G2B <= not G2B_L; -- convert inputs Y <= not Y_L; -- convert outputs U1: v3to8dec port map (G1,G2A,G2B,A,Y); end v74x138_c; Veton Këpuska

  15. VHDL entity description and internal structure Entityv74x138 Entityv74x138 G1 G1 Y_L[0:7] G1 G2A_L G2A_L not G2 Y_L[0:7] Y[0:7] not G2B_L G2B_L not G3 A[2:0] A[2:0] A[2:0] Veton Këpuska

  16. Dataflow definition of an active-high 3-to-8 decoder library IEEE; use IEEE.std_logic_1164.all; entity v3to8dec is port (G1,G2,G3: in STD_LOGIC; -- enable inputs A: in STD_LOGIC_VECTOR(2 downto 0); -- select inputs Y: out STD_LOGIC_VECTOR(0 to 7)); -- decoded outputs end v3to8dec; architecture v3to8dec_a of v3to8dec is signal Y_s: STD_LOGIC_VECTOR(0 to 7); begin with A select Y_s <= “10000000” when “000”, “01000000” when “001”, “00100000” when “010”, “00010000” when “011”, “00001000” when “100”, “00000100” when “101”, “00000010” when “110”, “00000001” when “111”, “00000000” when others; Y <= Y_s when (G1 and G2 and G3) = ‘1’ else “00000000”; end v3to8dec_a; Veton Këpuska

  17. Behavioral-style architecture definition for a 3-to-8 decoder architecture v3to8dec_b of v3to8dec is signal Y_s: STD_LOGIC_VECTOR(0 to 7); begin process(A,G1,G2,G3,Y_s) begin case A is when “000” => Y_s <= “10000000”; when “001” => Y_s <= “01000000”; when “010” => Y_s <= “00100000”; when “011” => Y_s <= “00010000”; when “100” => Y_s <= “00001000”; when “101” => Y_s <= “00000100”; when “110” => Y_s <= “00000010”; when “111” => Y_s <= “00000001”; when others => Y_s <= “00000000”; end case; if (G1 and G2 and G3) = ‘1’ then Y <= Y_s; else Y <= “00000000”; end if; end process; end v3to8dec_b; Veton Këpuska

  18. 4-to-16 decoder Decoder cascading Veton Këpuska

  19. 5-to-32 decoder More cascading Veton Këpuska

  20. Decoder Encoder Encoders vs. Decoders • One performs Inverse function of the other: Veton Këpuska

  21. Example of 8x3 binary encoder Y0 = I1 + I3 + I5 + I7 Y1 = I2 + I3 + I6 + I7 Y2 = I4 + I5 + I6 + I7 Binary Encoders Veton Këpuska

  22. Need priority in most applications • The problem with encoders presented in previous slide is that it can be used only when one input is active at a time. • When multiple requests can be made simultaneously the encoder gives undesirable results/outputs. • For example, if inputs I2 and I4 of 8-to-3 encoder are both 1; then the output is 110, the binary encoding of 6. • If encoder is used to request service form a device then this would produce an erroneous behavior (2 or 4 would be proper response but not 6). • An appropriate solution is to assign priority to the input lines, so that when multiple requests are asserted, the encoding device produces the number of the highest-priority requestor. Such a device is called a priority encoder. Veton Këpuska

  23. Priority Encoders Veton Këpuska

  24. Define intermediate variables H0-H7: Hi = 1 when Ii is the highest priority 1 input: H7 = I7 H6 = I6*I7’ H5 = I5*I6’*I7’ … H0 = I0*I1’*I2’*I3’*I4’*I5’*I6’*I7’ A2 = H4 + H5 + H6 + H7 A1 = H2 + H3 + H6 + H7 A0 = H1 + H3 + H5 + H7 IDLE = (I0+I1+I2+I3+I4+I5+I6+I7)’ = I0’*I1’*I2’*I3’*I4’*I5’*I6’*I7’ Logic symbol for a generic 8-input priority encoder 8-input priority encoder Veton Këpuska

  25. 74x148 8-input priority encoder • Active-low I/O • Enable Input • “Got Something” • Enable Output Veton Këpuska

  26. Logic Diagram of 74x148 Veton Këpuska

  27. 74x148 Truth Table Veton Këpuska

  28. Cascading priority encoders • 32-inputpriority encoder Veton Këpuska

  29. VHDL Program for a 74x148-like 8-input priority encoder. library IEEE; use IEEE.std_logic_1164.all; entity v74x148 is port (EI_L: in STD_LOGIC; I_L: in STD_LOGIC_VECTOR(7 downto 0); A_L: out STD_LOGIC_VECTOR(2 downto 0); EO_L: out STD_LOGIC; GS_L: out STD_LOGIC); end v74x148; architecture v74x148p of v74x148 is signal EI: STD_LOGIC; -- active-high version of input signal I: STD_LOGIC_VECOTR (7 downto 0); -- active-high version of inputs signal EO, GS: STD_LOGIC; -- active-high version of outputs signal A: STD_LOGIC_VECOTR (2 downto 0); -- active-high version of outputs begin process (EI_L, I_L, EI, E0, GS, I, A) variable j: INTEGER range 7 downto 0; begin EI <= not EI_L; -- convert input I <= not I_L; -- convert inputs E0 <= ‘1’; GS <= ‘0’; A <= ‘000’; if (EI = ‘0’) then E0 <= ‘0’; else for j in 7 downto 0 loop if I(j) = ‘1’ then GS <= ‘1’; E0 <= ‘0’; A <= CONV_STD_LOGIC_VECTOR(j,3); exit; end if; end loop; EO_L <= not E0; -- convert output GS_L <= not GS; -- convert output A_L <= not A; -- convert output end process; end v74x148p; Veton Këpuska

  30. VHDL function for converting INTEGER to STD_LOGIC_VECTOR function CONV_STD_LOGIC_VECTOR(ARG: INTEGER; SIZE: INTEGER) return STD_LOGIC_VECTOR is variable result: STD_LOGIC_VECTOR (SIZE-1 downto 0); variable temp: integer; begin temp := ARG; for I in 0 to SIZE-1 loop if (temp mod 2) = 1 then result(i) := ‘1’; else result(i) = ‘0’; end if; temp := temp / 2; end loop; return result; end; Veton Këpuska

  31. Inputs & Outputs Functional equivalent Multiplexers Veton Këpuska

  32. Example of 74x151 8-input multiplexer Veton Këpuska

  33. 74x151 truth table Veton Këpuska

  34. Other multiplexer varieties • 2-input, 4-bit-wide • 74x157 Veton Këpuska

  35. Multiplexers in VHDL • CASE statement is used to describe multiplexers behavior in VHDL. • Example of 4-input, 8-bit multiplexer is given in the next slide Veton Këpuska

  36. Dataflow VHDL program for a 4-input, 8-bit multiplexer library IEEE; use IEEE.std_logic_1164.all; entity mux4in8b is port( S: in STD_LOGIC_VECTOR(1 downto 0); -- Select inputs, 0-3 => A-D A,B,C,D: in STD_LOGIC_VECTOR(1 to 8);-- Data bus input Y: out STD_LOGIC_VECTOR(1 to 8) -- Data bus output ); end mux4in8b; architecture mux4in8b of mux4in8b is begin with S select Y <= A when “00”, B when “01”, C when “10”, D when “11”, (others => ‘U’) when others; -- this creates an 8-bit vector of ‘U’ end mux4in8b; Veton Këpuska

  37. Behavioral architecture for a 4-input, 8-bit multiplexer architecture mux4in8p of mux4in8b is begin process (S,A,B,C,D) begin case S is when “00” => Y <= A; when “01” => Y <= B; when “10” => Y <= C; when “11” => Y <= D; -- an 8-bit vector of ‘U’ when others => Y <= (others => ‘U’); end case; end process; end mux4in8p; Veton Këpuska

  38. Barrel Shifter • A barrel shifter is a combinational logic circuit with: • n data input, • n data outputs, and • A set of control inputs that specify how to shift the data between input and output. • A barrel shifter that is part of microprocessor CPU can typically specify: • direction of shift (left or right) • type of shift (circular, arithmetic, or logical) • amount of shift (typically 0 to n-1 bits). Veton Këpuska

  39. Barrel shifter design example • n data inputs, n data outputs • Control inputs specify number of positions to rotate or shift data inputs • Example: n = 16 • DIN[15:0], DOUT[15:0], S[3:0] (shift amount) • Many possible solutions, all based on multiplexers • Example: • Input: ABCDEFGHGIHKLMNOP • Control input is 0101 (5) • Output: FGHGIHKLMNOPABCDE Veton Këpuska

  40. Multiple Designs are Possible • Tradeoffs in the speed and the size of the circuit. Veton Këpuska

  41. 16-to-1 mux = 2 x 74x151 8-to-1 mux + NAND gate Example: 16 16-to-1 muxes Veton Këpuska

  42. VHDL behavioral description of a 6-function barrel shifter. library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_arith.all; entity barrel16 is port( DIN: in STD_LOGIC_VECTOR(15 downto 0); -- Data inputs S: in UNSIGNED(3 downto 0); -- Shift amount 0-15 C: in STD_LOGIC_VECTOR(2 downto 0); -- Mode control DOUT: out STD_LOGIC_VECTOR(15 downto 0); -- Data bus output ); constant Lrotate: STD_LOGIC_VECTOR := “000”; -- Define the coding of constant Rrotate: STD_LOGIC_VECTOR := “001”; -- the different shift modes constant Llogical: STD_LOGIC_VECTOR := “010”; -- shift in 0’s constant Rlogical: STD_LOGIC_VECTOR := “011”; -- shift in 0’s constant Larith: STD_LOGIC_VECTOR := “100”; -- replicate LSB constant Rarith: STD_LOGIC_VECTOR := “101”; -- replicate MSB end barel16; Veton Këpuska

  43. VHDL behavioral description of a 6-function barrel shifter (cont.) architecture barel16_behavioral of barel16 is subtype DATAWORD is STD_LOGIC_VECTOR(15 downto 0); function Vrol (D: DATAWORD; S: UNSIGNED) return DATAWORD is variable N: INTEGER; variable TMPD: DATAWORD; begin N := CONV_INTEGER(S); TMPD := D; for I in 1 to N loop TMPD := TMPD(14 downto 0) & TMPD(15); end loop; return TMPD; end Vrol; function Vror (D: DATAWORD; S: UNSIGNED) return DATAWORD is variable N: INTEGER; variable TMPD: DATAWORD; begin N := CONV_INTEGER(S); TMPD := D; for I in 1 to N loop TMPD := TMPD(0) & TMPD(15 downto 1); end loop; return TMPD; end Vrol; ... Veton Këpuska

  44. VHDL behavioral description of a 6-function barrel shifter (cont.) begin process (DIN, S, C) begin case C is when Lrotate => DOUT <= Vrol(DIN,S); when Rrotate => DOUT <= Vror(DIN,S); when Llogical=> DOUT <= Vsll(DIN,S); when Rlogical=> DOUT <= Vrll(DIN,S); when Larith => DOUT <= Vsla(DIN,S); when Rarith => DOUT <= Vsra(DIN,S); when others => null; end case; end process; End barrel16_behavioral; Veton Këpuska

  45. Comparators • Based on xor gate: Veton Këpuska

  46. 1-bit comparator 4-bit comparator Equality Comparators Veton Këpuska

  47. Logic diagram for 74x682 8-bit comparator Traditional logic symbol for the 74x682 8-bit comparator 8-bit Magnitude Comparator Veton Këpuska

  48. Derivation of additional conditions from 74x682 Veton Këpuska

  49. Comparators in VHDL library IEEE; use IEEE.std_logic_1164.all; entity vcompare is port( A,B: in STD_LOGIC_VECTOR(7 downto 0); EQ,NE,GT,GE,LT,LE: out STD_LOGIC ); end vcompare; architecture vcompare_arch of vcompare is begin process (A,B) begin EQ <= ‘0’; NE <= ‘0’; GT <= ‘0’; GE <= ‘0’; LT <= ‘0’; LE <= ‘0’; if A = B then EQ <= ‘1’; end if; if A /= B then NE <= ‘1’; end if; if A > B then GT <= ‘1’; end if; if A >= B then GE <= ‘1’; end if; if A < B then LT <= ‘1’; end if; if A <= B then LE <= ‘1’; end if; end process; end vcompare_arch; Veton Këpuska

  50. X Y Cin S Cout 0 0 0 0 0 0 0 1 1 0 0 1 0 1 0 0 1 1 0 1 1 0 0 1 0 1 0 1 0 1 1 1 0 0 1 1 1 1 1 1 Adders • Basic building block is “full adder” • 1-bit-wide adder, produces sum and carry outputs • Truth table: Veton Këpuska

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