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A 200-MSPS 6-Bit Flash ADC in 0.6-um CMOS

A 200-MSPS 6-Bit Flash ADC in 0.6-um CMOS. 班級 : 積體所碩一 學生 : 林義傑. Reference. D. Dalton, G. Spalding, H. Reyhani, T. Murphy, K. Deevy, M. Walsh, and P. Griffin,“A 200-MSPS 6-Bit Flash ADC in 0.6-μ m CMOS,” IEEE Trans. On Circuits and Systems-II , vol. 45, no. 11, pp. 1433-1444, Nov., 1998.

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A 200-MSPS 6-Bit Flash ADC in 0.6-um CMOS

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  1. A 200-MSPS 6-Bit Flash ADC in 0.6-um CMOS • 班級: 積體所碩一 • 學生:林義傑

  2. Reference D. Dalton, G. Spalding, H. Reyhani, T. Murphy, K. Deevy, M. Walsh, and P. Griffin,“A 200-MSPS 6-Bit Flash ADC in 0.6-μ m CMOS,” IEEE Trans. On Circuits and Systems-II, vol. 45, no. 11, pp. 1433-1444, Nov., 1998.

  3. Outline • The common ADC • A 200-MSPS 6-Bit Flash ADC • Measurement Results • Conclusion

  4. Introduce Application Conditions • Sample Rate • Sample Bit Length • Effective Number of Bits (ENOB) • Chip area • Power Consumption

  5. Introduction A/D converter • Nyquist rate A/D converter • High speed converter • middle speed converter • low speed converter • Oversampling A/D converter

  6. Nyquist sampling Rate fs ≥ 2 fin 取樣頻率與信號基頻之間關係

  7. The common ADC Architecture • Flash Architecture • Folding Architecture • Feedback Architecture • Pipelined Architecture

  8. PRML System Overvier

  9. Tradition FLASH ADC Architecture

  10. Fully differential 6-Bit Flash ADC

  11. Key requirement of the ADC

  12. ADC input circuitry

  13. NMOS followers driving 63 comparators

  14. Layout

  15. Measurement Result

  16. Measurement Result

  17. Compare with other circuit

  18. Conclusion

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