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DDR1 using AMBA Design ware Memory Controller interfacing with MICRON 16VDDF12864HY We use DDR1 and testing the design using Virtex-5 FPGA. HCLK(DDR CLK) = 75MHz , MCLK(2xHCLK) = 150MHz, 16-bit Interface.
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DDR1 using AMBA Design ware Memory Controller interfacing with MICRON 16VDDF12864HY • We use DDR1 and testing the design using Virtex-5 FPGA. • HCLK(DDR CLK) = 75MHz , MCLK(2xHCLK) = 150MHz, 16-bit Interface. • All the Timing control register, latency(2) are changed to run at 75MHz and controller is re initialized at the end before read/write is attempted. • Slide-3 (block diagram) • Signals highlighted are probed using Xilinx chip scope at respective points. • Few control signals are tapped before interface module, due to routing complexities, so all the probed signals are not 100% cycle matched on waveform, so the description of interface module is attached in slide3 for reference,(for ex RAS,CAS.. are tapped before DDR interface module and WR_DQS is tapped after the interface before moving to IO). • Slide-4(Read/Write), Slide-5(Write Zoomed), Slide-6(Read Zoomed) • Slide-7(Configuration after the 200us wait triggered when CKE goes high) • Issue – We do not see the memory responding back to the controller.
AMBA MCTL IFC DDR interface (write pipe adjustments). REFER NEXT SLIDE For More info DDR_CK MICRON DDR1 Memory MT16VDDF12864HY.. DDR_CK_n CLK_MCTL (DDR_CLK_O_SIG * 2) IO BUF WR_DQS[1:0] DQS_IO RD_DQS[1:0] DDR_CLK_O_SIG MCTL_RAS_n DDR_DOUT_VALID[1:0] MCTL_CAS_n MCTL_WE_n MCTL_SEL_n IDDR IO BUF DDR_RD_LDATA[15:0] MCTL_DOUT_VALID DQ_IO DDR_RD_UDATA[15:0] MCTL_CKE DDR_WR_DATA[15:0]
