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Research Summary of Oregon State University

Research Summary of Oregon State University. Patrick Chiang Email: pchiang@eecs.oregonstate.edu Website: http://e ecs.oregonstate.edu www.ece.oregonstate.edu. Summary. Overview of Oregon State My Current Research Interests High Frequency (> 20GHz) Serial Links

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Research Summary of Oregon State University

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  1. Research Summary of Oregon State University Patrick Chiang Email: pchiang@eecs.oregonstate.edu Website: http://eecs.oregonstate.edu www.ece.oregonstate.edu

  2. Summary • Overview of Oregon State • My Current Research Interests • High Frequency (> 20GHz) Serial Links • Low power (< 1Gbs/mW) signaling • High Sampling Rate (> 20GS/s), Low Resolution ADC • Tsinghua Research • Low Power(< 2mW), Low Voltage(< 1V) RF Receiver • Programmable, Redundant, Self-healing RF CircuitDesign with On-Die Calibration

  3. Life at Oregon State University • Location • Beautiful surroundings • Oregon is high tech center • Intel • Mentor Graphics • Synopsys Oregon State Stanford, Berkeley UCLA, Caltech Main Hall, OSU Mt. Hood, Oregon IntelHillsboro, Oregon

  4. Gabor Temes Un-Ku Moon Terri Fiez Karti Mayaram Andreas Weisshaar Raghu Settaluri Huaping Liu Zhongfeng Wang Mixed-Signal Faculty Patrick Chiang Pavan Hanumolu Self correcting RF/analog design in scaled technologies Substrate coupling Signal integrity, interconnects, packaging, passives Extensible communication & low power DSP architectures

  5. Why Oregon State Mixed-Signalis Recognized • VLSI Circuits Symposium 2006 • # of Papers – 111 • Oregon State – 9 • Berkeley – 7 • UCLA – 5 • UCSD – 2 • Stanford – 2 • MIT – 1 Top quality faculty • More than 500 journal and conference publications • More than 12 editors/associate editors • More than 5 books and 13 books chapters • 4 Fellows of the IEEE Top quality graduate students • Over 200 graduate students in mixed-signal integration Strong external collaboration • MIT, Illinois, Stanford, Berkeley, U Washington, Harvard National Semiconductor, Texas Instruments, Analog Devices, Intel, Cypress Semiconductor, AKM, Boeing, SRC, CDADIC, Crystal Semiconductor, Motorola, Silicon Labs, DARPA, AFRL, Honeywell, Tektronix, Sandia National Labs, Cadence “OSU has one of the nation’s leading research programs on analog and mixed-signal design.” Dave Hodges, former Dean of Engineering, UC Berkeley

  6. New Momentum for Growing Program • New Building, Sep. 2005 http://engr.oregonstate.edu/top25/building/

  7. Summary • Overview of Oregon State • My Current Research Interests • High Frequency (> 20GHz) Serial Links • Low power (< 1Gbs/mW) signaling • High Sampling Rate (> 20GS/s), Low Resolution ADC • Tsinghua Research • Low Power(< 2mW), Low Voltage(< 1V) RF Receiver • Programmable, Redundant, Self-healing RF CircuitDesign with On-Die Calibration

  8. IBM Processor y r o CPU CPU m e M From/to other High-speed I/Os subsystems (e.g. backplane) TransmitterOutput ReceiverInput Router Backplane(1m, FR4) 4Gb/s Low Power, Area Efficient Serial Links • Interconnection betweendifferent chips • Transmitter Equalization • Receiver Offset Cancellation 4Gb/s Transmitter Output, 1m 2000 0.25um Testchip 2001 0.25um Testchip • Ming-Ju E. Lee, William J. Dally, John W. Poulton, Patrick Chiang, Stephen F. Greenwood. An 84-mW 4Gb/s Clock and Data Recovery Circuit for Serial Link Applications. VLSI Circuits Symposium, Kyoto, Japan, June 2001, pp. 149-152. • Ming-Ju E. Lee, William Dally, Patrick Chiang. Low-Power Area-Efficient High-Speed I/O Circuit Techniques. IEEE Journal of Solid-State Circuits, November 2000, Vol. 35, No. 11, pp. 1591-1599. 4Gb/s Transmitter Output, Equalized 4Gb/s Transmitter Output

  9. 165mW / transmitter • 0.23mm^2 20Gb/s 0.13um CMOS Serial Link Transmitter Test Interface 10GHz PLL TestStructures PRBS Check PhaseInterpolators 700um RX DLL Clock Recovery TX TransmitterMuxing PRBS Gen Data Rate = 19.2Gb/s Jitter = 2.2ps/15.6ps RMS/pk-pk 1.1mm • Patrick Chiang, William J. Dally, Ming-Ju Edward Lee, Ramesh Senthinathan, Yangjin Oh, and Mark Horowitz. A 20Gb/s 0.13um CMOS Serial Link Transmitter Using an LC-PLL to Directly Drive the Output Multiplexer. IEEE Journal of Solid-State Circuits, Vol. 40, No. 4, April 2005, pp. 1004-1011. • Patrick Chiang, William J. Dally, Ming-Ju Edward Lee, Ramesh Senthinathan, Yangjin Oh, and Mark Horowitz. A 20Gb/s 0.13um CMOS Serial Link Transmitter Using an LC-PLL to Directly Drive the Output Multiplexer. 2004 Symposium on VLSI Circuits, June 15-19, 2004, pp. 272-275.

  10. 80mV 62mV 43ps 35ps 450um 350um Transmitter 500um 600um 33mV 62mV Receiver 35ps 37ps 20Gb/s 0.13um CMOS Transceiver • 361mW / transceiver • 0.46mm^2 • 20mV input sensitivity 72mV 36ps Unequalized(no channel loss) Equalized(no channel loss) • 2-Tap Equalization • Demultiplexing Receiver Unequalized(-6.5dB @ 10GHz) Equalized(-6.5dB @ 10GHz)

  11. State of the Art: Ken Poulton, ISSCC 2003 High Sampling Rate, Low Resolution A/D Converters • High sampling rate, low resolution ADCs important for: • Ultrawideband RF • High speed serial links • 10G Ethernet of copper

  12. New Architecture Conventional Architecture Proposed New ADC • Modifications to thesis receiver architecture • Front-end samplers • Downstream amplifiers • Calibration circuits compensating timing offset • > 10x power reduction • > 10x area reduction

  13. Summary • Overview of Oregon State • My Current Research Interests • High Frequency (> 20GHz) Serial Links • Low power (< 1Gbs/mW) signaling • High Sampling Rate (> 20GS/s), Low Resolution ADC • Tsinghua Research • Low Power(< 2mW), Low Voltage(< 1V) RF Receiver • Programmable, Redundant, Self-healing RF CircuitDesign with On-Die Calibration

  14. PreviousWork ThisWork Tsinghua Research: Super-Regenerative Receiver • Reduced Power Consumption vs. Conventional • High sensitivity due to Q-enhanced LC Filter

  15. Pin < -190dBm Pin < -170dBm Pin < -150dBm Pin = no signal Super-Regenerative Input Sensitivity OscillationTime Increasing Q ReceiverVoltage Input

  16. Summary • Overview of Oregon State • My Current Research Interests • High Frequency (> 20GHz) Serial Links • Low power (< 1Gbs/mW) signaling • High Sampling Rate (> 20GS/s), Low Resolution ADC • Tsinghua Research(with Dr. Baoyong Chi) • Low Power(< 2mW), Low Voltage(< 1V) RF Receiver • Programmable, Redundant, Self-healing RF CircuitDesign with On-Die Calibration

  17. Low Noise AmplifierAbidi, ISSCC 2006 Analog / RF Design in Deep Submicron • Transistor scaling advantages: • Ubiquitous transistors • Transistor fT • SOC Integration • Disadvantages: • Process variation • Inaccurate device/parasitic modeling • Increased design time / cost • Un-optimum fabricated silicon • Analog / RF Design has not changed!

  18. Example: 2.4GHz LNA S11, S22 • SS,TT,FF Process Skew, 30mV Threshold Variation • 180nm UMC, RF/mixed-signal process • Variation MUCH worse than simulated • Not including metal/dielectric variation • Not RF design in 90nm/65nm logic process

  19. Proposing Programmable, ParallelRF Circuit Design • Transistors are free • Create parallel, digitally switchable RF Circuits • Novelty: Digital On-Die Calibration • Exact device models / parasitic extraction unnecessary • Design time reduction • Design benefit from DeepSubmicron CMOS

  20. Conclusion • Oregon State is a great place to pursue a graduate degree • I am looking for intense, bright students to start my research group • Questions? • Email: pchiang_calstan@yahoo.com • Email: pchiang@ece.oregonstate.edu

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