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D-Type Flip Flops

D-Type Flip Flops. Benchmark Companies Inc PO Box 473768 Aurora CO 80047. Lecture Overview. D Flip-Flops Asynchronous Input Sample Flip-Flop Applications.

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D-Type Flip Flops

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  1. D-Type Flip Flops Benchmark Companies Inc PO Box 473768 Aurora CO 80047

  2. Lecture Overview • D Flip-Flops • Asynchronous Input • Sample Flip-Flop Applications

  3. Gated D-Type Latch The D-Latch is an expanded version of an RS Flip Flop. The symbol shown is used to represent this type of flip-flop.

  4. Gated D-Type LatchIt is also known as transparent latch, data latch, or simply a gated latch

  5. Gated D-Type Latch It has a data input and an enable signal (sometimes named clock or control).

  6. D-Type Flip-FlopsThe D flip-flop can be interpreted as a primitive delay line or zero-order hold, since the data is posted at the output one clock cycle after it arrives at the input

  7. D Q Q CLK   D 0 1 Q n+1 0 1 D Flip-FlopThe Data Table below illustrates the output Q(n+1) with respect to the Data (D) clocked (CLK) into the latch.

  8. D Q Q CLK   D 0 1 Q n+1 0 1 CLK D Q D Flip-FlopAs illustrated below the clock pulse into the Flip Flop (FF) will synchronize the output.

  9. Application of D Flip-Flops • Data Storage • Counters & State Machine Designs • Logic Synchronizing • Divide By Circuits

  10. Logic SynchronizingSynchronizing data is done by clocking all D-Type FF with the same clock. This puts data on A,B and C at the same time.

  11. Divide By Circuit using a D Flip-FlopThe D-Type FF can be configured to divide the pulse in half by configuring the circuit below. SIG_IN SIG_OUT

  12. D Q Q Positive Edge Triggered D Q Q Negative Edge Triggered Types of D Flip-Flops The trigger happens during the designed trigger edge.

  13. D Q Q Positive Level Triggered D Q Q Negative Level Triggered Types of D Flip-Flops The trigger happens during the designed trigger level

  14. CLK X X X   P-SET 0 1 0 1 1 CLR 1 0 0 1 1 D X X X 0 1 Q n+1 1 (preset) 0 (clear) ? (illegal) 0 1 P-SET D Q Q D Flip-Flop w/ Preset & Clear CLR Types of D Flip-Flops Asynchronous Inputs The FF can be designed with Preset (P-SET) or clear (CLR)

  15. End of Lesson

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