Flip-Flops

1. Flip-Flops Section 4.3 Mano & Kime

2. D CLK Q !Q 0 1 0 1 1 1 1 0 X 0 Q0 !Q0 D Latch S !S D Q CLK !Q !R R Note that Q follows D when the clock in high, and is latched when the clock goes to zero.

3. D Pulse-narrowing circuit CLK D NCK Q !Q D CLK Q !Q 0 1 0 1 1 1 1 0 X 0 Q0 !Q0 0 0 1 1 1 0 X 0 Q0 !Q0 D Flip-Flop S !S Q NCK !Q !R R

4. Pulse-Narrowing Circuit

5. D Q CLK !Q D CLK Q !Q 0 0 1 1 1 0 X 0 Q0 !Q0 D Flip-Flop Positive edge triggered D gets latched to Q on the rising edge of the clock.

6. D Q CLK !Q D Flip-Flop pulse width CLK setup time hold time y z propagation delay

7. Making a positive edge-triggered D Flip-Flop from Master-Slave D Latches x y z input output D Q D Q master slave CLK’ E E CLK CLK CLK’ x y z

8. SR Master-Slave Flip-Flop S R CLK Q !Q 0 0 1 Q0 !Q0 Store 0 1 1 0 1 Reset 1 0 1 1 0 Set 1 1 1 1 1 Disallowed X X 0 Q0 !Q0 Store

9. J-K Flip-Flop J K CLK Q !Q 0 0 Q0 !Q0 0 1 0 1 1 0 1 0 1 1 Toggle X X 0 Q0 !Q0 J Q CLK !Q K

10. Master-Slave J-K Flip-Flop

11. Master-Slave J-K Flip-Flop

12. D-Type Positive Edge-Triggered Flip-Flop

13. Positive Edge-Triggered J-K Flip-Flop