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Flip-Flops. Basic concepts. Flip-Flops. A flip-flop is a bi-stable device: a circuit having 2 stable conditions (0 or 1) 3 classes of flip-flops latches: outputs respond immediately while enabled (no timing control) pulse-triggered flip-flops: outputs response to the triggering pulse
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Flip-Flops Basic concepts
Flip-Flops • A flip-flop is a bi-stable device: a circuit having 2 stable conditions (0 or 1) • 3 classes of flip-flops • latches: outputs respond immediately while enabled (no timing control) • pulse-triggered flip-flops: outputs response to the triggering pulse • edge-triggered flip-flops: outputs responses to the control input edge A. Yaicharoen
Conventions • The circuit is set means output = 1 • The circuit is reset means output = 0 • Flip-flops have two output Q and Q’ or (Q and Q) • Due to time related characteristic of the flip-flop, Q and Q’ (or Q) are usually represented as followed: • Qt or Q: present state • Qt+1 or Q+: next state A. Yaicharoen
4 Types of Flip-Flops SR flip-flop JK flip-flop D flip-flop T flip-flop A. Yaicharoen
SR Latch An SR (or set-reset) latch consists of • S (set) input: set the circuit • R (reset) input: reset the circuit • Q and Q’ output: output of the SR latch in normal and complement form Application example: a switch debouncer A. Yaicharoen
SR latch A. Yaicharoen
An application of the SR latch Effects of contact bounce. A switch debouncer. A. Yaicharoen
latch A. Yaicharoen
Gated SR latch (c) A. Yaicharoen
Gated D latch A. Yaicharoen
Timing Consideration When using a real flip-flop, the following information is needed to be considered: • propagation delay (tpLH, tpHL) - time needed for an input signal to produce an output signal • minimum pulse width (tw(min)) - minimum amount of time a signal must be applied • setup and hold time (tsu, th) - minimum time the input signal must be held fixed before and after the latching action A. Yaicharoen
Propagation delays in an SR latch A. Yaicharoen
Timing diagram for an SR latch A. Yaicharoen
Minimum pulse width constraint A. Yaicharoen
Timing diagram for a gated D latch A. Yaicharoen
Unpredictable response in a gated D latch A. Yaicharoen
Master-slave SR flip-flop A. Yaicharoen
Timing diagram for a master-slave SR flip-flop A. Yaicharoen
Master-slave JK flip-flop A. Yaicharoen
Timing diagram for master-slave JK flip-flop A. Yaicharoen
Master-slave D flip-flop A. Yaicharoen
Master-slave T flip-flop A. Yaicharoen
Positive-edge-triggered D flip-flop A. Yaicharoen
Timing diagram for a positive-edge-triggered D flip-flop A. Yaicharoen
Negative-edge-triggered D flip-flop A. Yaicharoen
Asynchronous Inputs • do not require the presence of a control signal • preset (PR) - set the flip-flop • clear (CLR) - reset the flip-flop • useful to bring a flip-flop to a desired initial state A. Yaicharoen
Positive-edge-triggered D flip-flop with asynchronous inputs A. Yaicharoen
Positive-edge-triggered JK flip-flop A. Yaicharoen
Positive-edge-triggered T flip-flop A. Yaicharoen
Master-slave JK flip-flop with data lockout A. Yaicharoen
Characteristic Equations • algebraic descriptions of the next-state table of a flip-flop • constructing from the Karnaugh map for Qt+1 in terms of the present state and input A. Yaicharoen
Characteristic equations A. Yaicharoen