Flip Flops

1. Flip Flops

2. Flip Flops • Flip-flops serve as the elementary units for memory in digital systems. Two features are needed: • 1. The circuit must be able to “hold” either state (a high or low output) and not simply reflect the input at any given time. • 2. But in some circumstances, we must be able to change (to “set” and “reset”) the values.

3. Remembrance of states past • The way in which the previous state information is held is different for different types of memory • In DRAM (dynamic random access memory), the state (1 or 0) is held by a charge (or lack thereof) remaining on a capacitor • Charges tend to leak off of capacitors, which is why DRAM must be periodically refreshed

4. SRAM • In SRAM (static random access memory) the history dependence is achieved via a feedback mechanism • Feedback: the return of part of the output to the input of a mechanism, process or system (Random House Dictionary) • SRAM does not need refreshing, making it faster, but it is more expensive; typically it is reserved for caching and other high-speed situations

5. RS Flip Flop feedback

6. RS Flip Flop • The Q output is inverted and fed back in as an input • Similarly the Q’ output is inverted and fed back in as an input • As suggested by the names Q and Q’, these outputs are supposed to be inverses of one another

7. The hold operation • The S=0, R=0 is the hold “state”, the flip flop keeps its previous outputs • Imagine Q=1 and Q’=0, • Then Not Q’ (which is 1) is ORed with S giving a 1 for the Q output • Then Not Q (which is 0) is ORed with R giving a 0 for the Q’ output • The output is the same as the input (no change)

8. The hold operation • The S=0, R=0 is the hold “state”, the flip flop keeps its previous outputs • Imagine Q=0 and Q’=1, • Then Not Q’ (which is 0) is ORed with S giving a 0 for the Q output • Then Not Q (which is 1) is ORed with R giving a 1 for the Q’ output • The output is the same as the input (no change)

9. The set operation • The S=1, R=0 is the set “state”, the flip flop force Q=1 • Imagine Q=0 and Q’=1, • Then Not Q’ (which is 0) is ORed with S giving a 1 for the Q output • Then Not Q (which is now 0) is ORed with R giving a 0 for the Q’ output • The Q output is forced to be (set to) 1

10. The set operation • The S=1,R=0 is the set “state”, the flip flop forces Q=1 • Imagine Q=1 and Q’=0, • Then Not Q’ (which is 1) is ORed with S giving a 1 for the Q output • Then Not Q (which is 0) is ORed with R giving a 0 for the Q’ output • The Q output is forced to be (set to) 1

11. The reset operation • The S=0,R=1 is the reset “state”, the flip flop forces Q=0 • Imagine Q=0 and Q’=1, • Then Not Q’ (which is 0) is ORed with S giving a 0 for the Q output • Then Not Q (which is 1) is ORed with R giving a 1 for the Q’ output • The Q output is forced to be (reset to) 0

12. The reset operation • The S=0,R=1 is the reset “state”, the flip flop forces Q=0 • Imagine Q=1 and Q’=0, • Then Not Q’ (which is 1) is ORed with S giving a 1 for the Q output • Then Not Q (which is now 0) is ORed with R giving a 1 for the Q’ output • Then Not Q’ (which is now 0) is ORed with S giving a 0 for the Q output • The Q output is forced to be (reset to) 0

13. The undesired operation • The S=1,R=1 is the undesired “state” • Imagine Q=0 and Q’=1, • Then Not Q’ (which is 0) is ORed with S giving a 1 for the Q output • Then Not Q (which is now 0) is ORed with R giving a 1 for the Q’ output • And so on • The Q and Q’ outputs are equal, which is undesired

14. Level clocking

15. Level clocking • Adding an additional layer of AND gates and an extra input makes the flip flop “clocked” • What used to be the S input is now S ANDed with CLK, so the set action is now obtained only when S=1 AND CLK=1 • This helps control when the setting occurs and keeps this action in sync with other operations occurring in the circuit

16. Edge triggering

17. Edge Triggering • Feeding the outputs of one clocked RS flip flop into a second flip flop in which the clock input is inverted results in an edge-triggered flip flop • The first flip flop acts as a level clocked flip flop, that is, setting and resetting occur only when the CLK input is 1

18. Edge triggering (cont.) • During this period, the second RS flip flop is getting the inverse of the CLK and so is in the no change state • When the CLK goes to 0, the first flip flop goes into its no change state and the second flip flop can be set or reset

19. Edge triggering • What is setting or resetting the second flip flop are the outputs of the first flip flop and they are held fixed • This way the inputs to the second flip flop can not vary through the course of the clock’s cycle • Whatever they were when the clock switched is what is important

20. JK Flip Flop

21. Making an RS into a JK • Recall that the R=1, S=1 input into an RS flip flop puts one into the undesired state • An additional feedback mechanism turns this undesired state of the RS flip flop into the “toggle” state of the JK flip flop

22. JK • The inputs into the first AND gate are now • J (used to be S), CLK and Q’ for the upper • K (used to be R), CLK and Q for the lower • Since Q and Q’ are inverses, at most one of the AND gates will yield a 1

23. The toggle state • If J and K and the CLK are all 1, the the outcome is determined by Q and Q’ • If Q=1 and Q’=0, then the lower AND gate will produce a 1 and Q’ will be made equal to 1 and Q will be set to 0 (just the opposite of what they were) • This is called the toggle state.