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High Speed Digital Systems Lab June 2008

A cceleration of E conomic C alculation. Black & Scholes model Acceleration. Developers: Ayal Ozer and Eyal Efrat Mentor: Michael Yampolsky. High Speed Digital Systems Lab June 2008. Acceleration of Economic Calculation Agenda. Motivation Theoretic Background Project Objectives

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High Speed Digital Systems Lab June 2008

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  1. Acceleration of Economic Calculation Black & Scholes model Acceleration Developers: Ayal Ozer and Eyal Efrat Mentor: Michael Yampolsky High Speed Digital Systems Lab June 2008

  2. Acceleration of Economic CalculationAgenda • Motivation • Theoretic Background • Project Objectives • Method of Operation • System Inputs & Outputs • System performance • Hardware vs. Software • Benchmark • Time Table

  3. Acceleration of Economic CalculationMotivation • World trade is more dynamic • There’s too much data to process in standard Hardware & Software Because time is money!

  4. Acceleration of Economic CalculationTheoretic Background • What is an option? • Which options are we going to work with? • What is the Black & Scholes model?

  5. Acceleration of Economic CalculationProject Objectives • Real time B&S calculation provides a great advantage in capital markets • Using specialized hardware could accelerate the calculation time of the B&S value by a factor of hundreds

  6. Acceleration of Economic CalculationModus operandi – method of operation • Compute the Black & Scholes value of the options in the MAOF index using a hi-speed FPGA and parallelizing the calculation process • Create a user interface which will display a table with live data and the B&S value of each option.

  7. Acceleration of Economic CalculationSystem Inputs INPUT Financial info about options of the MAOF • http://www.tase.co.il • Financial server OUTPUT • B&S calculation for the options • The difference between the option and it’s B&S value

  8. Acceleration of Economic CalculationSystem Performance • The name of the game isSPEED • The calculation must be quick, hence the choice of a high speed FPGA platform. • The aim is to increase calculation speed by a factor of hundreds.

  9. Acceleration of Economic CalculationHardware vs. Software • The B&S model will be initially be calculated by software using C++ • The B&S model will then be implemented using an Altera Startix II FPGA mounted on a GiDEL ProcStar II board.

  10. Acceleration of Economic CalculationBenchmark ? = FPGA Software Test vector

  11. Acceleration of Economic CalculationTime Table

  12. Acceleration of Economic Calculation Questions?

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