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Lecture 4 Design Rules,Layout and Stick Diagram

Lecture 4 Design Rules,Layout and Stick Diagram. Pradondet Nilagupta pom@ku.ac.th Department of Computer Engineering Kasetsart University. Acknowledgement.

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Lecture 4 Design Rules,Layout and Stick Diagram

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  1. Lecture 4Design Rules,Layout and Stick Diagram Pradondet Nilagupta pom@ku.ac.th Department of Computer Engineering Kasetsart University

  2. Acknowledgement • This lecture note has been summarized from lecture note on Introduction to VLSI Design, VLSI Circuit Design all over the world. I can’t remember where those slide come from. However, I’d like to thank all professors who create such a good work on those lecture notes. Without those lectures, this slide can’t be finished. 204424 Digital Design Automation

  3. Roadmap for the term: major topics • VLSI Overview • CMOS Processing & Fabrication • Components: Transistors, Wires, & Parasitics • Design Rules & Layout • Combinational Circuit Design & Layout • Sequential Circuit Design & Layout • Standard-Cell Design with CAD Tools • Systems Design using Verilog HDL • Design Project: Complete Chip 204424 Digital Design Automation

  4. n well P substrate wafer Review - CMOS Mask Layers • Determine placement of layout objects • Color coding specifies layers • Layout objects: • Rectangles • Polygons • Arbitrary shapes • Grid types • Absolute (“micron”) • Scaleable (“lambda”) 204424 Digital Design Automation

  5. Mask Generation • Mask Design using Layout Editor • user specifies layout objects on different layers • output: layout file • Pattern Generator • Reads layout file • Generates enlarged master image of each mask layer • Image printed on glass • Step & repeat camera • Reduces & copies image onto mask • One copy for each die on wafer • Note importance of mask alignment 204424 Digital Design Automation

  6. Symbolic Mask Layers • Key idea: • Reduce layers to those that describe design • Generate physical layers as needed • Magic Layout Editor: "Abstract Layers” • metal1 (blue) - 1st layer metal (equiv. to physical layer) • Poly (red) - polysilicon (equivalent to physical layer) • ndiff (green) - n diffusion (combination of active, nselect) • ntranistor (green/red crosshatch) - combined poly, ndiff • pdiff (brown) - p diffusion (combination of active, pselect) • ptransistor (brown/red crosshatch) - combined poly, pdiff • contacts: combine layers, cut mask 204424 Digital Design Automation

  7. About Magic • Scalable Grid for Scalable Design Rules • Grid distance: l (lambda) • Value is process-dependent: l = 0.5 X minimum transistor length • Painting metaphor • Paint squares on grid for each mask layer • Layers to interact to form components (e.g. transistors) 204424 Digital Design Automation

  8. Mask Layers in Magic • Poly (red) • N Diffusion (green) • P Diffusion (brown) • Metal (blue) • Metal 2 (purple) • Well (cross-hatching) • Contacts (X) 204424 Digital Design Automation

  9. Cursor Box Paint (poly) Paint (ntransistor) Paint (pdiff) Magic User-Interface • Graphic Display Window • Cursor • Box - specifies area to paint • Command window (not shown) • accepts text commands:paint poly:paint red:paint ndiff:paint green:write • prints error & status messages 204424 Digital Design Automation

  10. Layer Interaction in Magic • Transistors - where poly, diffusion cross • poly crosses ndiffusion - ntransistor • poly crosses pdiffusion - ptransistor • Vias - where layers connect • Metal 1 connecting to Poly - polycontact • Metal 1 connecting to P-Diffusion (normal) - pdc • Metal 1 connecting to P-Diffusion (substrate contact) - psc • Metal 1 connecting to N-Diffusion (normal) - ndc • Metal 1 connecting to N-Diffusion (substrate contact) - nsc • Metal 1 connecting to Metal 2 - via 204424 Digital Design Automation

  11. nsc p-transistor metal1 nwell pdc polycontact metal1 poly polycontact poly metal1 psc ndc ndc ntransistor Magic Layers - Example 204424 Digital Design Automation

  12. Why we need design rules • Masks are tooling for manufacturing. • Manufacturing processes have inherent limitations in accuracy. • Design rules specify geometry of masks which will provide reasonable yields. • Design rules are determined by experience. 204424 Digital Design Automation

  13. Manufacturing problems • Photoresist shrinkage, tearing. • Variations in material deposition. • Variations in temperature. • Variations in oxide thickness. • Impurities. • Variations between lots. • Variations across a wafer. 204424 Digital Design Automation

  14. Transistor problems • Varaiations in threshold voltage: • oxide thickness; • ion implanatation; • poly variations. • Changes in source/drain diffusion overlap. • Variations in substrate. 204424 Digital Design Automation

  15. Wiring problems • Diffusion: changes in doping -> variations in resistance, capacitance. • Poly, metal: variations in height, width -> variations in resistance, capacitance. • Shorts and opens: 204424 Digital Design Automation

  16. Oxide problems • Variations in height. • Lack of planarity -> step coverage. metal 2 metal 2 metal 1 204424 Digital Design Automation

  17. Via problems • Via may not be cut all the way through. • Undesize via has too much resistance. • Via may be too large and create short. 204424 Digital Design Automation

  18. MOSIS SCMOS design rules • Designed to scale across a wide range of technologies. • Designed to support multiple vendors. • Designed for educational use. • Ergo, fairly conservative. 204424 Digital Design Automation

  19.  and design rules •  is the size of a minimum feature. • Specifying  particularizes the scalable rules. • Parasitics are generally not specified in units 204424 Digital Design Automation

  20. Design Rules • Typical rules: • Minumum size • Minimum spacing • Alignment / overlap • Composition • Negative features 204424 Digital Design Automation

  21. Types of Design Rules • Scalable Design Rules (e.g. SCMOS) • Based on scalable “coarse grid” - l (lambda) • Idea: reduce l value for each new process, but keep rules the same • Key advantage: portable layout • Key disadvantage: not everything scales the same • Not used in “real life” • Absolute Design Rules • Based on absolute distances (e.g. 0.75µm) • Tuned to a specific process (details usually proprietary) • Complex, especially for deep submicron • Layouts not portable 204424 Digital Design Automation

  22. SCMOS Design Rules • Intended to be Scalable • Original rules: SCMOS • Submicron: SCMOS-SUBM • Deep Submicron: SCMOS-DEEP • Pictorial Summary: Book Fig. 2-24, p. 27 • Authoritative Reference: www.mosis.org 204424 Digital Design Automation

  23. SCMOS Design Rule Summary • Line size and spacing: • metal1: Minimum width=3l, Minimum Spacing=3l • metal2: Minimum width=3l, Minimum Spacing=4l • poly: Minimum width= 2l, Minimum Spacing=2l • ndiff/pdiff: Minimum width= 3l, Minimum Spacing=3l, minimum ndiff/pdiff seperation=10l • wells: minimum width=10l, min distance form well edge to source/drain=5l • Transistors: • Min width=3l • Min length=2l • Min poly overhang=2l 204424 Digital Design Automation

  24. SCMOS Design Rule Summary • Contacts (Vias) • Cut size: exactly 2l X 2l • Cut separation: minimum 2l • Overlap: min 1l in all directions • Magic approach: Symbolic contact layer min. size 4l X 4l • Contacts cannot stack (i.e., metal2/metal1/poly) • Other rules • cut to poly must be 3l from other poly • cut to diff must be 3l from other diff • metal2/metal1 contact cannot be directly over poly • negative features must be at least 2l in size • CMP Density rules (AMI/HP subm): 15% Poly, 30% Metal 204424 Digital Design Automation

  25. Design Rule Checking in Magic • Design violations displayed as error paint • Find which rule is violated with ":drc why” Poly must overhang transistor by at least 2 (MOSIS rule #3.3) 204424 Digital Design Automation

  26. Scaling Design Rules • Effects of scaling down are positive • See book, p. 78-79 - if “everything” scales, scaling circuit by 1/x increases performance by x • Problem: not everything scales proportionally 204424 Digital Design Automation

  27. Aside - About MOSIS • MOSIS - MOS Implementation Service • Rapid-prototyping for small chips • Multi-project chip idea - several designs on the same wafer • Reduced mask costs per design • Accepts layout designs via email • Brokers fabrication by foundries (e.g. AMI, Agilent, IBM, TSMC) • Packages chips & ships back to designers • Our designs will use AMI 1.5µm process (more about this later) 204424 Digital Design Automation

  28. Aside - About MOSIS • Some Typical MOSIS Prices (from www.mosis.org) • AMI 1.5µm “Tiny Chip” (2.2mm X 2.2mm) $1,080 • AMI 1.5µm 9.4mm X 9.7mm $17,980 • AMI 0.5µm 0-5mm2 $5,900 • TSMC 0.25µm 0-10mm2 $15,550 • TSMC 0.18µm 0-7mm2 $24,500 • TSMC 100-159mm2 $63,250 + $900 X size • MOSIS Educational Program (what we use) • AMI 1.5µm “Tiny Chip” (2.2mm X 2.2mm) FREE* • AMI 0.5mm “Tiny Chip” (1.5mm X 1.5mm) FREE* *sponsored by Semiconductor Industry Assn., Semiconductor Research Corp., | AMI, Inc., DuPont Photomasks, and MOSIS 204424 Digital Design Automation

  29. Layout Considerations • Break layout into interconnected cells • Use hierarchy to control complexity • Connect cells by • Abutment • Added wires • Key goals: • Minimize size of overall layout • Meet performance constraints • Meet design time deadlines 204424 Digital Design Automation

  30. Hierarchy in Layout • Chips are constructed as a hierarchy of cells • Leaf cells - bottom of hierarchy • Root cells - contains overall cell • Example - hypothetical “UART” • Pad frame - “ring” that contains I/O pads • Core - contains logic organized as subcells • Shift register • FSM • Other cells 204424 Digital Design Automation

  31. Hierarchy Example • Root Cell: UART 204424 Digital Design Automation

  32. Wires metal 3 6 metal 2 3 metal 1 3 pdiff/ndiff 3 poly 2 204424 Digital Design Automation

  33. Transistors 2 2 3 3 1 5 204424 Digital Design Automation

  34. Vias • Types of via: metal1/diff, metal1/poly, metal1/metal2. 4 4 1 2 204424 Digital Design Automation

  35. Metal 3 via • Type: metal3/metal2. • Rules: • cut: 3 x 3 • overlap by metal2: 1 • minimum spacing: 3 • minimum spacing to via1: 2 204424 Digital Design Automation

  36. Tub tie 4 1 204424 Digital Design Automation

  37. Spacings • Diffusion/diffusion: 3 • Poly/poly: 2 • Poly/diffusion: 1 • Via/via: 2 • Metal1/metal1: 3 • Metal2/metal2: 4 • Metal3/metal3: 4 204424 Digital Design Automation

  38. Overglass • Cut in passivation layer. • Minimum bonding pad: 100 m. • Pad overlap of glass opening: 6 • Minimum pad spacing to unrelated metal2/3: 30 • Minimum pad spacing to unrelated metal1, poly, active: 15 204424 Digital Design Automation

  39. Stick diagrams (1/3) • A stick diagram is a cartoon of a layout. • Does show all components/vias (except possibly tub ties), relative placement. • Does not show exact placement, transistor sizes, wire lengths, wire widths, tub boundaries. 204424 Digital Design Automation

  40. Stick Diagrams (2/3) • Key idea: "Stick figure cartoon" of a layout • Useful for planning layout • relative placement of transistors • assignment of signals to layers • connections between cells • cell hierarchy 204424 Digital Design Automation

  41. Stick Diagrams (3/3) 204424 Digital Design Automation

  42. Example - Stick Diagrams (1/2) Alternatives - Pull-up Network Circuit Diagram. Pull-Down Network (The easy part!) Complete Stick Diagram 204424 Digital Design Automation

  43. Example - Stick Diagrams (2/2) 204424 Digital Design Automation

  44. Dynamic latch stick diagram VDD in out VSS phi phi’ 204424 Digital Design Automation

  45. Stick Diagram XOR Gate Examples 204424 Digital Design Automation

  46. Hierarchical Stick Diagrams • Define cells by outlines & use in a hierarchy to build more complex cells 204424 Digital Design Automation

  47. Cell Connection Schemes • External connection - wire cells together • Abutment - design cells to connect when adjacent • Reflection, mirroring - use to make abutment possible 204424 Digital Design Automation

  48. Example: 2-input multiplexer • First cut: 204424 Digital Design Automation

  49. Sticks design of multiplexer • Start with NAND gate: 204424 Digital Design Automation

  50. NAND sticks VDD a out b VSS 204424 Digital Design Automation

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