Clk

1. 0->1 1 0->1 1 A A O 0 O 1 B B SI SI SI D D D Sen Sen Sen Q Q Q A B C scan_enable Clk

2. capture launch shift shift Clk scan_enable dead cycle dead cycle

3. clk_func scan_enable clk_test ClkA Div2 PLL1 ClkB Div4 clk_pll_ref scan clock switches ClkC Div6 PLL2 Div8 clk_func

4. 0 0 1 1 D Q CK CL D D Q Q CK CK scan clock switch scan_enable clk_func clk_test ClkA clk_scan scan_capture_enable clk_func scan_stuck_testmode scan_speed_testmode D Q D Q scan_stuck_testmode scan_speed_testmode CK CK CL CL Dual-stage synchronizer or closely placed back-to-back FFs clk_test CL CL rst_n 2 pulse generation clk_func Enable logic for broadside at-speed pulses: clk_func launch + capture pulses enabled for 2 clk_func cycles, triggered on rising edge of clk_test.

5. D D D D D Q Q Q Q Q CK CK CK CK CK CL CL CL CL CL D D D D D D Q Q Q Q Q Q CK CK CK CK CK CK D Q D Q clk_test CK CK CL CL CL CL rst_n 2 pulse generation clk_func D Q D Q CK CK CL CL CL CL 3 pulse generation scan_num_pulse_sel[N:0] D Q D Q N - 3 CK CK CL CL N - 3 CL CL N pulse generation

6. rst_n PSB scan_capture_enable[0] scan_in Q D scan_enable Den clk_test CK PSB scan_capture_enable[1] Q D Den Data enabled (Den) FFs on scan chain guarantee scan_capture_enable outputs are held during capture cycles. Connect scan_capture_enable output port to respective scan_capture_enable input port on scan clock switch. CK PSB scan_capture_enable[X] Q D Den CK scan_out

7. shift capture launch shift ClkA FA ClkB ClkC clk_test scan_enable v1 v3 v5 v6 v7 v2 v9 v4 v10 v8 shift capture launch shift ClkA ClkB FB ClkC clk_test scan_enable v17 v11 v15 v16 v13 v12 v14 v19 v20 v18