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OIF SPI System Packet Interface

OIF SPI System Packet Interface. Applied Micro Circuits Corporation. Transmit Link Layer Device. SERDES Framer Interface (SFI). SERDES Framer Interface (SFI). Optical Interface. System Packet Interface (SPI). Receive Link Layer Device. PHY Device. SERDES Device and Optics. FEC.

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OIF SPI System Packet Interface

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  1. OIF SPI System Packet Interface Applied Micro Circuits Corporation

  2. TransmitLink Layer Device SERDES Framer Interface (SFI) SERDES Framer Interface (SFI) Optical Interface System Packet Interface (SPI) Receive Link Layer Device PHY Device SERDES Device and Optics FEC Data Status Data Data Data Clock Clock Status T F I Data Data Data Clock Clock Data TDM Fabric to Framer Interface (TFI) OIF Electrical Specifications OR

  3. TransmitLink Layer Device Receive Link Layer Device System Packet Interface (SPI-n) S y s t e m t o O p t i c s System Packet Interface (SPI) Transmit Interface PHY Device Data Status Data Status Receive Interface O p t i c s t o S y s t e m

  4. SPI-3: OIF SPI3-01.0 S y s t e m t o O p t i c s TX TXREFCK TXREFCK TFCLK Link Layer NP ATM SAR D C TDATA [31:0] Framer TXDATA [15:0] TENB Serdes TMOD[1:0] TXDSC TPRTY TSOP TXDCK TEOP TERR TXCKSRC TSX DTPA[3:0] A SONET/SDH OC-48 4xOC-12 16xOC-3 B STPA PTPA TADR[1:0] RXDATA [15:0] RXDSC RFCLK RENB RXDCK RDAT[31:0] A B RMOD[1:0] RXS RRPRTY RVAL RSOP REOP RXREFCK RERR RSX RX RXREFCK O p t i c s t o S y s t e m Support up to 2.5Gb/s bi-directional data throughput 8 bit or 32 bit interface options LVCMOS signals; point to point operation In-band addressing

  5. SPI-3: OIF SPI3-01.0 S y s t e m t o O p t i c s TX TXREFCK TXREFCK TFCLK Link Layer NP ATM SAR D C TDATA [31:0] Framer TXDATA [15:0] TENB Serdes TMOD[1:0] TXDSC TPRTY TSOP TXDCK TEOP TERR TXCKSRC TSX DTPA[3:0] A B Supports: Packet over SONET ATM over SONET Frame Relay over SONET STPA PTPA TADR[1:0] RXDATA [15:0] RXDSC RFCLK RENB RXDCK RDAT[31:0] A B RMOD[1:0] RXS RPRTY RVAL RSOP REOP RXREFCK RERR RSX RX RXREFCK O p t i c s t o S y s t e m 8 bit operation supports 1xOC-12 (622 MB/s) Data transfer independent of line bit rate Transfers ATM cells, packets including IP, FR, etc. Flow control on interface Error indication signal

  6. SPI-4 Phase 1: OIF-SPI4-01.0 S y s t e m t o O p t i c s TX TXREFCK TXREFCK TXCLK D Link Layer NP ATM SAR C TXDATA [63:0] Framer TXDATA [15:0] TXADDR[N-1:0] Serdes TXSIZE[2:0] TXDSC TXPRTY[3:0] SONET/SDH OC-192 10GE WAN/LAN 4xOC-48 16xOC-12 64xOC-3 256xSTS-1 TXSOCP TXDCK TXEOP TXERR TXCKSRC TXVALID TXSTART A B TXFULL[3:0] RXDATA [15:0] RXCLK RXDATA[63:0] RXDSC RXADDR[N-1:0] RXDCK RXSIZE[2:0] RXPRTY[3:0] A B RXSOCP RXS RXEOP RXERR RXVALID RXREFCK RXSTART RXFULL[3:0] RX RXREFCK O p t i c s t o S y s t e m Support up to 10GB/s bi-directional data throughput First generation; 200 MHz operation implementable in FPGA technology 64 bit interface @ 200 MHz (lower rate operation supported) HSTL Class 1 signals; source synchronous clocking; point to point operation Out-of-band addressing

  7. SPI-4 Phase 1: OIF-SPI4-01.0 S y s t e m t o O p t i c s TX TXREFCK TXREFCK TXCLK D Link Layer NP ATM SAR C TXDATA [63:0] Framer TXDATA [15:0] TXADDR[N-1:0] Serdes TXSIZE[2:0] Supports: POS/HDLC EoS/X.86 ATM 10GE LAN 10GE WAN TXDSC TXPRTY[3:0] TXSOCP TXDCK TXEOP TXERR TXCKSRC TXVALID TXSTART A B TXFULL[3:0] RXDATA [15:0] RXCLK RXDATA[63:0] RXDSC RXADDR[N-1:0] RXDCK RXSIZE[2:0] RXPRTY[3:0] A B RXSOCP RXS RXEOP RXERR RXVALID RXREFCK RXSTART RXFULL[3:0] RX RXREFCK O p t i c s t o S y s t e m 4x16bit mode of operation for 4xOC-48 multi-phy applications Supports Packet over SONET (POS); Ethernet over SONET (EoS/X.86); ATM over SONET; 10GE WAN/LAN PHY (IEEE 802.3ae)

  8. SPI-4 Phase 2 S y s t e m t o O p t i c s TXREFCK TXREFCK TX D C Link Layer NP ATM SAR Framer TXDATA [15:0] Serdes SONET/SDH OC-192 10GE WAN/LAN 4xOC-48 16xOC-12 64xOC-3 256xSTS-1 TDCLK TXDSC TDAT [15:0] TCTL TXDCK TSCLK TXCKSRC TSTAT[1:0] A B RXDATA [15:0] RXDSC RXDCK RDCLK RDAT[15:0] A B RCTL RXS RSCLK RSTAT[1:0] RXREFCK RX RXREFCK O p t i c s t o S y s t e m Support up to 10GB/s bi-directional data throughput Next generation technology; faster and narrower interface 16 bit LVDS interface @ 800 MHz (622 MHz minimum operation)

  9. SPI-4 Phase 2: OIF-SPI4-02.0 S y s t e m t o O p t i c s TXREFCK TXREFCK D C TX Link Layer NP ATM SAR Framer TXDATA [15:0] Serdes TDCLK TXDSC TDAT [15:0] TCTL Supports: POS/HDLC EoS/X.86 ATM 10GE LAN 10GE WAN TXDCK TSCLK TXCKSRC TSTAT[1:0] A B RXDATA [15:0] RXDSC RXDCK RDCLK RDAT[15:0] A B RCTL RXS RSCLK RSTAT[1:0] RXREFCK RX RXREFCK O p t i c s t o S y s t e m Supports Packet over SONET (POS); Ethernet over SONET (EoS/X.86); ATM over SONET; 10GE WAN/LAN PHY (IEEE 802.3ae) FIFO status out of band; 2 options for status signal rate (full and 1/4 speed)

  10. TransmitLink Layer Device Receive Link Layer Device SPI-5: OIF-SPI5-01.0 System Packet Interface System Packet Interface (SPI) SERDES Framer Interface (SFI-5) OC-768 System Interface for Physical and Link Layer Devices Transmit Interface PHY Device Data SERDES Device Status Data Status Receive Interface

  11. SPI-5: OIF-SPI5-01.0 System Packet Interface Transmit Interface PHY Device Point-to-point connection (i.e. single PHY / single Link Layer device) Transmit Link Layer Device TDCLK TDAT [15:0] Point-to-point connection Support for 256 ports TCTL TSTAT Receive Link Layer Device RDCLK RDAT [15:0] RCTL RSTAT Receive Interface Support for 256 ports with address extension to 2144 ports

  12. SPI-5: OIF-SPI5-01.0 System Packet Interface Transmit Interface PHY Device Control words carry In-band Port Address, start/end of packet indication & error-control mode TDCLK Transmit Link Layer Device TDAT [15:0] TCTL TSTAT 2.488 Gb/s Receive Link Layer Device RDCLK RDAT [15:0] RCTL RSTAT Receive Interface Data transfer segmented in bursts that are multiples of 16 words (32 bytes) 2.488 Gb/s minimum data rate per line on data path

  13. SPI-5: OIF-SPI5-01.0 System Packet Interface Transmit Interface Independent transmit/receive pool status channel PHY Device Transmit Link Layer Device TDCLK TDAT [15:0] TCTL TSTAT Receive Link Layer Device RDCLK RDAT [15:0] RCTL RSTAT Receive Interface Operates at the same clock rate as the data path

  14. Optional Max 16 bytes 32n Bytes (except End-of-Packet Transfers) SPI-5: OIF-SPI5-01.0 System Packet Interface Anatomy of a Transfer Address Control Word Address Data Word(s) Payload Control Word Payload Data Words Control Word

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