CMPT 250 Computer Architecture

1. CMPT 250 Computer Architecture Instructor: Yuzhuang Hu yhu1@cs.sfu.ca

2. Midterm • The midterm is schedule on June 17th, 17:30-19:30 pm. It covers the following: • VHDL Programming. • Number Systems. • Sequential Circuit Design. This includes State-Machine Diagrams, ASM chart, control unit, data path, etc. • The Simple Single-Cycle Computer. Its Datapath, the Control Word, Instruction Formats, Single Cycle Hardwired Control, etc.

3. Block Diagram for a Single-Cycle Computer

4. Instruction Specifications for the Simple Computer

5. Control Unit of the Single Cycle Simple Computer • We have described the design of its datapath. • The block diagram for this computer has a hardwired control unit that fetches and executes an instruction in a single clock cycle. • We do not write to the instruction memory, making it appear in this model to be a combinational rather than a sequential component.

6. The Program Counter (PC) • The PC provides the instruction address to the instruction memory. • The PC is updated in each clock cycle. The behaviour of the PC is determined by the opcode, N, and Z.

7. T ruth T a ble for Instruction Decoder Logic Instruction Bits Contr ol W o r d Bits Instruction Function Type 15 14 13 9 M B M D R W M W P L J B B C Function unit operations using 0 0 0 X 0 0 1 0 0 X X registers Memory read 0 0 1 X 0 1 1 0 0 X X Memory write 0 1 0 X 0 X 0 1 0 X X Function unit operations using 1 0 0 X 1 0 1 0 0 X X register and constant Conditional branch on zero (Z) 1 1 0 0 X X 0 0 1 0 0 Conditional branch on negative (N) 1 1 0 1 X X 0 0 1 0 1 Unconditional J ump 1 1 1 X X X 0 0 1 1 X Instruction Decoder • The instruction decoder is a combinational circuit that provides all of the control words for the datapath, based on the contents of the fields of the instruction.

8. Instruction Decoder contd. • The 13th, 14th and 15th bits of the instruction are set to 1 respectively, to distinguish the memory read, memory write and constant involved instructions from the register only instructions. • For this reason MB=15th bit, MD=13th bit, and the 14th bit is involved in generating MW. • There is some additional logic to prevent RW and MW to be 1 at the same time.

9. Instruction Decoder contd. • The 15th bit of the instructions is used mainly for jumping and branching instructions. However to distinguish them from the instructions involving constants, the 14th bit is also needed to generate PL. • BC uses the 9th bit. JB uses the 13th bit, however as PL=1 when JB=1, there is no conflict with MD. • For conditional branching, it is required that FS=0000. That’s the reason PL is involved in generating FS.

10. Instruction Opcode DR SA SB 5 – 3 8 – 6 2 – 0 15 14 13 12 11 10 9 16 – 14 19 – 17 13 – 11 10 9 – 6 5 4 3 2 1 0 AA DA BA MB FS MD RW MW PL JB BC Control word Instruction Decoder Logic

11. Six Instructio ns for the Sin g le-Cycle Comp uter Operation Symb ol ic co de na m e Fo rm a t D e s c r ip ti on Fu nc ti on MB MD R W MW PL J B BC [ ] ¬ [ ] 1000 010 ADI I mme diate A dd immediate R DR R SA zf I (2:0) 1 0 1 0 0 0 0 + operand [ ] ¬ [ ] [ ] 0010 000 LD Register Load mem o ry R DR M R SA 0 1 1 0 0 1 0 c ont e n t in to reg i s t er 0100 000 ST Register Store re gister 0 1 0 1 0 0 0 [ ] [ ] ¬ [ ] M R SA R SB c onten t in memory [ ] ¬ [ ] 0001 110 SL Register Shift left R DR sl R SB 0 0 1 0 0 1 0 [ ] ¬ [ ] 0001 011 NO T R egister Comple ment R DR R SA 0 0 1 0 0 0 1 reg i s t er 1100 000 BRZ J ump/Branch If R [SA] = 0, branch If R[ SA] = 0, 1 0 0 0 1 0 0 ¬ to PC + se AD PC P C se AD , + ¹ ¬ If R[S A ] 0, PC PC 1 + Sample Instructions

12. Shortcomings of the Single-Cycle Computer • The single cycle computer can not perform more complex operations. For example, unsigned binary multiplications. • The single cycle computer has two distinct 16-bit memories, one for instructions and one for data. • Every instruction, no matter it is simple or complex (e.g., jmp), is executed in a clock cycle. Therefore It has a lower limit on the clock period.

13. Worst-Case Delay Path in Single-Cycle Computer ns PC 0.2 Instruction Memory 4.0 0.6 Register File (Read) 0.2 MUX B 4.0 FU or Data Memory 0.2 MUX D 0.6 Register File (Write)

14. Store Instructions and Data in a Single Memory • Datapath : a single memory, and an MUX M. Add 8 temporary registers to the register file. • Control Unit: • Instruction Register (IR) to store the instruction fetched from the memory. • Control State. The control unit is now a sequential circuit. • Control Logic : different control words. Branch logic is moved to here.

16. NS PS IL Ne xt State Action Code Action Code Gives next state Hold PC 00 No load 0 of Control State Inc PC 01 Load IR 1 Register Branch 10 J ump 11 Control Word Format for Multi-Cycle Computer 27 24 23 22 21 20 17 16 13 12 9 8 7 4 3 2 1 0 I M M R M M NS PS AX BX FS DX L B D W M W • The addressing of the registers needs 4 bits (DX, AX, BX). Sequencing Datapath Sequence Control NS: next state PS: control PC IL: control IR

17. Sequential Control Design • Now the computer has two stages: instruction fetch (INF stage) and instruction execution (EX0 stage). ns ns PC IR 0.2 0.2 INF EX0 0.6 0.2 MUX M Register File (Read) 4.0 Memory 0.2 MUX B 0.2 IR 4.0 FU or Data Memory 0.2 MUX D 0.6 Register File (Write)

18. I n st ruction Speci ficationsfor the Simple Comput er - Part 1 St a t u s Instr u ctio n O pc ode Mnem on ic Form a t D escrip tion Bits ¬ Move A 0000000 MO V A RD ,RA R [DR] R[SA ] N , Z ¬ Increment 0000001 INC R D , RA R[DR] R [ SA] + 1 N , Z ¬ Add 0000010 ADD R D , RA,RB R [DR] R[SA ] + R[ SB] N , Z ¬ - Subtr a ct 0000101 SUB R D , RA,RB R [DR] R[SA ] [ SB] N , Z R ¬ - D e crement 0000110 DEC R D , RA R[DR] R[SA ] 1 N , Z ¬ Ù AND 0001000 AND R D , RA,RB R [DR] R[SA ] R[SB ] N ,Z ¬ Ú O R 0001001 OR RD ,RA,RB R[DR] R[SA ] R[SB ] N ,Z ¬ Å Exclusive OR 0001010 XOR R D , RA,RB R [DR] R[SA ] R[SB] N , Z ¬ R[SA ] NO T 0001011 NO T R D , RA R[DR] N, Z Instruction Specifications

19. Partial State Machine Diagram for Multiple-Cycle Computer

20. Deriving Logic Expressions • For PC <- PC +1, we must set PS to 01. • We can write PS(0) = EX0·MOVA + EX0 ∙ INC + EX0 ∙ ADD + … + EX0·BRZ·(not Z). • Each combination of state, opcode, and condition codes where the signal should be 1 introduces a product term to the final expression.

21. Multiplication in the Multiple-Cycle Computer • For simple instructions, we need more time to finish them in the multi-cycle computer. • Multiplication shows the advantage. • Assume multiplication in the function unit needs 10 ns. For the single cycle-cpu, the clock cycle must be increased to 15.8 ns. • The clock cycle would remain 5.8 ns, if we give one more clock cycle for multiplication.

22. State Diagram for Multiplication INF IR <- M[PC] Multiply R[SA]*R[SB] EX0 R[DR] <- R[SA]*R[SB], PC <- PC + 1 IMUL1

23. Register Indirect Instructions • R[DR] <- M[M[R[SA]]]. INF IR <- M[PC] Opcode = 0010001 R8 <- M[R[SA]] EX0 Opcode = 0010001 EX1 R[DR]<-R8, PC <- PC+1

24. Partial State Machine Diagram for Right-Shift and Left-Shift Multiple Instructions

25. Micro-programmed Control • A control unit with its binary control values stored as words in memory is called a micro-programmed control. • Each word in the control memory contains a microinstruction that specifies one or more micro-operations for the system. • The micro-program is usually fixed at the system design time and so is stored in ROM.

26. CAR: Control Address Register.

27. THANKS!