CMPT-250 Computer Architecture

1. CMPT-250 Computer Architecture Instructor: Yuzhuang Hu yhu1@cs.sfu.ca

2. Course Timetable • Lectures: Wednesday 17:30-20:20, HCC 2510 • Labs: Thursday 17:30-18:20, HCC 7050 • Midterm, Final: TBA • Office Hours: Instructor: Friday 14:30-16:30, HCC 2134 TA: TBA

3. Contact Information • Instructor: Yuzhuang Hu Email: yhu1@cs.sfu.ca Office Hours: Friday 2:30pm-4:30pm Office: HC 2134 Phone: 778-782-8740 • TA: Zhiyong Lu Email: zhiyong@cs.sfu.ca Office Hours: TBA

4. Marking Scheme • 4 Assignments + Labs, 30% Late Penalty: -20% per day • Midterm, 20% • Final, 50%

5. What is Computer Architecture? • Instruction Set Architecture: the actual programmer visible instruction set. • Implementation • Organization: high level aspects of a computer’s design. • Hardware: specifics of a machine, e.g., the detailed logic design.

6. A Personal Computer Screen Hard drive Keyboard Drive Controller Bus Interface Graphics Adapter RAM Processor CPU, FPU, MMU Internal Cache External Cache

7. Von Neumann Architecture • Stored program concept. Memory Control Unit Data Path CPU Input/Output

8. Binary Numbers Voltage(Volts) • Digital signals are in fact analog. 0 and 1 are represented by voltage ranges. 1 1.0 0.5 0 0.0 Time Time

9. Number Systems • Decimal numbers are of base 10, e.g., 724 = 7 ×102 + 2×101 + 4×100 • Binay numbers are of base 2, e.g., (1101)2 = 1×23 + 1×22 + 0×21 + 1×20 = 13

10. Convert a decimal number N to binary • Loop remainder = N mod 2 add remainder to the left of the result N = N / 2 • An example: remainder result 2 14 0 0 2 7 1 10 2 3 1 110 1 1 1110

11. Truth Table of Full Adder Inputs Outputs C S X Y Z 0 0 0 0 0 0 0 1 0 1 0 1 0 0 1 0 1 1 1 0 1 0 0 0 1 1 0 1 0 1 1 1 0 1 0 1 1 1 1 1 Full Adder • A full adder considers a carry in bit.

12. Binary Subtraction • Method 1: First compare the subtrahend with the minuend. Then subtract the smaller from the larger. • Method 2: Directly subtract the subtrahend from the minuend. An example: Borrowsinto: 11000 Minuend: 10011 Subtrahend: -11110 10101 Difference: Correct Difference: -01011

13. Complements • 2’s complement of a binary number M is defined to be the number 2n – M. • 1’s complement of a binary number M is defined to be the number (2n – 1) – M . • 1’s complement of M can be obtained by subtracting 1 each digit from 1. 2’s complement of M = 1’s complement of M + 1.

14. Subtraction Using 2s Complement • Task: compute M – N, where M and N are two n-digit unsigned numbers. • Add the 2s complement of N to M. This performs M + (2n – N) = M – N + 2n. • If M ≥ N, discard the end carry, leaving M – N. • If M < N, the sum equals 2n – (N – M). Do a correction by taking the 2s complement of the sum and place a minus sign in front.

15. Signed Numbers • A binary number M can be represented by: • Signed-magnitude system: Add 0 to the left of M if M ≥ 0, and add 1 to the left of M if M < 0. For example, +7 = 0111, -7 = 1111. • Signed-complement system: Add 0 to the left of M if M ≥ 0, and add 1 to the left of the 2s complement of M if M < 0. For example, +7 = 0111, -7 = 1001.

16. Signed Binary Addition and Subtraction • The subtraction of M – N under the signed-magnitude representation: similar to the unsigned subtraction using 2’s complements. • The subtraction of M – N under the complement representation : obtained from the addition of the two numbers, including their sign bits. A carry out of the sign bit position is discarded. No comparison or subtraction is needed.

17. Signed Binary Subtraction contd. • When M is positive, and N is negative: This performs M + 2n + (2n – N)=M – N + 2n+1. If M - N ≥ 0, then the sign bit is 0 after discarding the carry. If M - N < 0, there is no carry out and the sign bit is 1. • It can be similarly argued when M is negative, and N is positive. -6 11111010 +6 00000110 +13 00001101 -13 11010011 +7 -7 00000111 11111001

18. Pitfalls: Overflow! • Overflow occurs when the sum takes more than n+1 bits. Two examples: • An overflow condition can be detected by observing the carry into the sign bit position and the carry out of the sign bit position. +70 0 1000110 -70 1 0111010 +83 0 1010000 -80 1 0110000 +150 -150 1 0010110 0 1101010

19. Overflow Detection Logic • An overflow occurs if the above mentioned two carries are not equal. V Cn-1 Cn N-bit Adder/Subtractor C

20. A Hardware Description Language: VHDL • A hardware description language (HDL) is any computer language for formal description of digital logic and electronic circuits. • HDL represents extensive parallel operations, whereas most programming languages represent serial operations. • VHDL stands for VHSIC Hardware Description Language (Very-High-Speed Integrated Circuits).

21. Entity Declarations in VHDL • entity full_addr is • port ( • c_in : in std_logic; • x : in std_logic; • y : in std_logic; • c_out : out std_logic; • sum : out std_logic • ); • end full_addr;

22. Truth Table of Full Adder Inputs Outputs C S X Y Z 0 0 0 0 0 0 0 1 0 1 0 1 0 0 1 0 1 1 1 0 0 1 1 0 0 1 0 1 0 1 1 1 0 1 0 1 1 1 1 1 Describing Behaviour in VHDL x sum Full Adder • architecture behav of full_addr is • begin • -- Your VHDL code defining the model • c_out <= (x and y) or (x and c_in) or (y and c_in) after 2 ns; • Sum <= x xor y xor c_in after 2 ns; • end behav; y c_out c_in

23. Describing Structure in VHDL • architecture structure of full_addr is • signal s1, s2, s3:std_logic; • Begin • G1:xor_3 port map(INA=>c_in, INB=>x, INC=>y, Y=>sum); • G2:and_2 port map(INA=>c_in,INB=>x, Y=>s1); • G3:and_2 port map(INA=>x,INB=>y, Y=>s2); • G4:and_2 port map(INA=>c_in,INB=>y, Y=>s3); • G5:or_3 port map(INA=>s1,INB=>s2, INC=>s3,Y=>c_out); • end structure;

24. Signals in VHDL • Signals are used in VHDL to interconnect components. • Signals have propagation delays. They behave like some real wires. • Each signal can have only one source.

25. Discrete Event Time Model • We need to simulate VHDL programs to verify whether the models we built are correct. • In a circuit digital signals change their values concurrently. VHDL simulates the passage of time of the signals in discrete events.

26. Concurrent Statements in VHDL • Concurrent-Signal-Assignment Statements: sum <= x xor y xor c_in after 2 ns; • Process-Statements: SUMPROC: process ( x, y, c_in) begin sum <= x xor y xor c_in after 2 ns; end process SUMPROC;

27. Concurrent Statements Contd. • Component-Initiation-Statements: G1:xor_3 port map(INA=>c_in, INB=>x, INC=>y, y=>sum); • An xor gate with 3 inputs would be instantiated, and its inputs would be wired with x, y, and c_in.

28. Signal Transactions and Events • When a signal assignment occurs, VHDL will treat it as a transaction and schedule the real assignment in some later time. • An event of a signal happens when the signal changes its value. 0 ns 0 ns 2 ns 2 ns 4 ns t1 t2 t3 t4 t5

29. Some Examples of Generating Transactions • The current time is 5ns, after executing S <= ‘0’ after 10ns; The transaction list would be: • The current time is 16ns, after executing S <= ‘1’, ‘0’ after 10ns; The transaction list would be: 15 ns 0 26 ns 16 ns 1 0

30. Initialization Phase • All signals are given initialization values. • The simulation time is set to 0. • All processes are executed until they suspend. When executing each signal assignment statement, a transaction on that signal will be generated .

31. A Simulation Cycle • First Stage: the transactions with the earliest time will be removed from the list and executed. The simulation time will be forwarded to that time. • Second Stage: when an event occurs in the first stage, all processes sensitive to the corresponding signal are executed. This means new transactions may be inserted to the list.

32. Test Bench • A test bench is a VHDL program designed to test your entities. The entities will be instantiated in the test bench. An example: entity tb_fa is end tb_fa; architecture behav of tb_fa is signal x1, y1, c_in1, c_out1 :std_logic; begin x1 <= ‘0’; y1 <= ‘1’; c_in1 <= ‘0’; UUT: full_addr port map(x=>x1, y=>y1, c_in=>c_in1, c_out=>cout1); end behav;

33. Variables in VHDL • The simulation cycles do not apply to variables in VHDL. As in any other programming language, the change on a variable after executing a statement is immediately effective. • In contrast, assignments on signals are not immediately visible for later sequential statements. A pitfall: s1 <= ‘0’; ………….. if s1=‘0’ then ………….. It won’t give the answer you want.

34. THANKS!