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Research Progress Fall 2009 - Present

Research Progress Fall 2009 - Present. Kevin Dwan June 25, 2010. UCLA. NEMS Project. Collaborators: UCLA Dejan Markovic UC Berkeley Elad Alon Tsu-Jae King Liu MIT Vladimir Stojanovic. Goals: Automation Innovative Logic. UCLA. Design Rule Checker (DRC).

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Research Progress Fall 2009 - Present

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  1. Research ProgressFall 2009 - Present Kevin Dwan June 25, 2010 UCLA

  2. NEMS Project Collaborators: UCLA Dejan Markovic UC Berkeley Elad Alon Tsu-Jae King Liu MIT Vladimir Stojanovic • Goals: • Automation • Innovative Logic UCLA

  3. Design Rule Checker (DRC) Automate verification process • CLICKR2: • 2 Routing Layers • 10 Total Layers • On the order of microns • SEMATECH: • “3” Routing Layers • 15 Total Layers • Special Layer Rules UCLA

  4. Encounter Layout automation • SEMATECH: • 3 usable routing layers • “2” device types • Shared masks with CMOS process • Implement “special vias” Electrode ViaContact M2 CMOS Via1 M1 CMOS UCLA

  5. Circuits • Asynchronous Circuits • Balloon Latches Muller Pipeline Shift Latch C C C4 C2 C3 C1 C C En D Q En D Q En D Q En D Q C3 C2 C1

  6. C Circuits • Muller C Element Muller Pipeline C Element

  7. Synthesis Design automation Behavioral Verilog Synthesis Structural Verilog PnR Flow Layout

  8. Synthesis Design automation • Implementation: • Define cells in standard cell library • Specify logical and timing behavior • Challenges: • Tool is designed for CMOS • Optimize for timing

  9. Synthesis Design automation • Proposed Solutions: • Specify Complex Combinational Blocks in library • Requires complementary inputs • Get tool to recognize tri-state behavior

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