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Status of SOI Pixel

Status of SOI Pixel. Mar. 18, 2009 @SuperBell PXD Mtg. Yasuo Arai (KEK) yasuo.arai@kek.jp http://rd.kek.jp/project/soi/. 1. Recent Progress. Second 0.2um SOI MPW run was submitted on February. 'SVD Amp/Memory' by Piotr Kapusta 'Vertical Integration Test' by LBNL/KEK

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Status of SOI Pixel

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  1. Status of SOI Pixel Mar. 18, 2009 @SuperBell PXD Mtg. Yasuo Arai (KEK) yasuo.arai@kek.jp http://rd.kek.jp/project/soi/ 1

  2. Recent Progress • Second 0.2um SOI MPW run was submitted on February.'SVD Amp/Memory' by Piotr Kapusta'Vertical Integration Test' by LBNL/KEK • LBNL Fine Analog SOI Pixel Result

  3. Feb. 2009 Submissin

  4. R&D of Amp/Memory chip for SVD with SOI technology Piotr Kapusta (Institute of Nuclear Physics, Krakow) preamp: output range +- 0.6V, input +-10MIP shaper: peaking time ~20ns pipeline: differential analog memory controlled by shift register fifo: separate analog memory with digital pointers control clk: 40MHz clock power supply: 0, -2.2V

  5. SOI SVD amp for Super Belle 2.4 x 2.4 mm2

  6. 6

  7. LDRD-SOI-1 Analog Pixels: Resolution Determine analog pixel spatial resolution by scan with pulsed 1060 nm laser focused on ~5mm spot; Change laser power to simulate different cluster S/N conditions; Reconstruct position using charge center-of-gravity; SOI analog 10 mm pixels demonstrate ~ 1 mm resolution m.i.p. MB et al. to appear on NIM

  8. ZyCube + OKI + KEK/LBNL Vertical Integration Use ZyCube m-bump bonding (~5 um pitch) technique. • Higher Functionality in each pixel. • Increase of material budget is minimum. 8

  9. Vertical Integration 9

  10. Vertical Integration Lower Chip Upper Chip

  11. Summary 11 2nd SOI MPW run was submitted last month First test circuit for the SupeBelle SVD amp/memory chip was submitted. Position resolution of 1 um is demonstrated by LBNL. We are also developing vertical integration technology which increase the functionality of the pixel.

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