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Development of SOI pixel sensor

Development of SOI pixel sensor. 28 Sep., 2006 Hirokazu Ishino (Tokyo Institute of Technology) for SOIPIX group. Outline. Motivation Introduction to the SOI detector performance of the SOI pixel TEG summary and plan. SOIPIX collaborators.

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Development of SOI pixel sensor

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  1. Development of SOI pixel sensor 28 Sep., 2006 Hirokazu Ishino (Tokyo Institute of Technology) for SOIPIX group

  2. Outline • Motivation • Introduction to the SOI detector • performance of the SOI pixel TEG • summary and plan

  3. SOIPIX collaborators KEK Detector Technology Project : [SOIPIX Group] Y. Arai(*)、Y. Ikegami、Y. Ushiroda、Y. Unno、O. Tajima、T. Tsuboyama、S. Terada、M. Hazumi、H. IkedaA、K. HaraB、H. IshinoC、T. KawasakiD、H. MiyakeEGary VarnerF, Elena MartinF, Hiro TajimaG,M. OhnoH, K. FukudaH, H. KomatsubaraH, J. IdaH KEK、JAXAA、U. TsukubaB、TITC、Niigata U.D、Osaka U.E, U. HawaiiF, SLACG, OKI Elec. Ind. Co.H

  4. Motivation • Vertex detectors play an essential role in particle physics • precise decay position measurements of the heavy quarks and leptons • Silicon On Insulator (SOI) is one of the techniques usable for future high energy experiments. • radiation hard • no parasitic NPNP structure, therefore no latch-ups. • thin active transistor, insensitive to SEU • can be a pixel detector w/o bump bonding • high-resistive handle wafer for radiation detection

  5. + − − + + − − + + − + − SOI detector design

  6. Overview of our SOI detector • Fully-Depleted CMOS SOI fabricated by OKI Electric Industry Co. Ltd. • commercial technology with 150nm rule • thin Si layer (~20nm) + metal gate • OKI adopts Unibond wafers from SOITEC, France • Top Si: Cz, ~18Ωcm, p-type, ~40nm thickness • Buried Oxide (BOX): 200nm thickness • handle wafer: Cz, high-resistive with > 1kΩ • no type assignment, however, identified by I-V measurements, shown later. • original thickness 650mm, thinned to 350mm and plated with Al (200nm).

  7. SOI wafer production (UNIBONDTM, SOITEC)

  8. SOI pixel process step flow • After Gate stack formation SOI Box 650um Handling wafer • Box Window photo lithography and etching Handling wafer • Source/Drain Implantation followed by S/D annealing and Salicidation n+ p+ Handling wafer • 1st ILD (interlayer dielectrics) filling and CMP planarization Handling wafer

  9. SOI pixel process step flow • Contact etching Handling wafer • Contact plug filling and 1st Metal formation 650um Handling wafer • 3 ~ 5Metal formation followed by Backside polishing and Al coating p+ n+ 250~350um Handling wafer Al

  10. Diode TEG Metal contact & p+ implant Al

  11. I-V characteristics of the handle wafer n+ - BACK |Current (A)| P+ - BACK BIAS (V) BIAS (V) substrate is N-type ~700Ωcm ~6✕1012 cm-3

  12. SOI TEG submitted in 2005 • 2.5 x 2.5 mm2 Chips • Transistor • p-MOS and n-MOS transistors of different parameters • the characteristics are measured • radiation test has been performed • Circuit • preamp, Q2T etc. • Strip • Silicon strip sensor for studying its basic performance • pixel • 32 x 32 matrix of 20 x 20 mm2 pixels • correlated double sample circuit • reset -> integrate -> readout

  13. Pixel TEG 6" MPW wafer 2.5 mm (chip) 20 mm(pixel)

  14. Pixel TEG CMOS Active Pixel Sensor Type 20 mm x 20 mm 32 x 32 pixels

  15. Pixel layout Window for Light Illumination (5.4 x 5.4 um2) p+ junction Storage Capacitance (100 fF)

  16. Pixel IV character Iback(mA) Vbreak ~ 100 V Hot Spot observed with infrared camera Vback(V) I = 40 A, T = 1 min corner of the bias ring  Smooth the corner and move the ring inward at next submission.

  17. Pixel detector image Plastic Mask Laser (670 nm) Vdet = 10 V Exposure Time = 7 ms

  18. Pixel detector signal of b rays from 90Sr Vdet = 10 V Wdepletion ~ 44 m Q ~ 3500 e(0.6 fC) Expected signal amplitude was observed for b-ray.

  19. Back gate effect Threshold Voltage (V) Back Gate Back gate Bias (V) Signal disappears at 16V Consistent with SPICE simulation.

  20. Back gate effect simulation NMOS D = (80, 5, 2 m) BOX (200 nm) Bulk: n- (~6 x 1012 cm-3) (5 mm wide p+, 1 x 1020 cm-3) 350mm ENEXSS : 3D TCAD Simulator Backbias (0-100 V) The p+ implant near the NMOS can reduces the back gate effect.

  21. Summary and Plan • We have started R&D of the SOI pixel detector with OKI Elec. Ind.Co. • A pixel detector with a 32 x 32 matrix of 20 x 20 mm2 pixels has been fabricated and tested. • Photo images are taken successfully • beta rays are successfully detected. • Back gate effect can be removed by placing p+ implant near the transistors. • the distance and shape are being optimized using ENEXSS 3D TCAD simulator • We will submit next TEG on Dec.

  22. backup

  23. n+ contact Contact & Sheet Resistance Hi-R (> 1k Wcm) Std. wafer (p+, ~13 Wcm) p+ contact [Sheet R] n+ : 33 W/square p+ : 136 W/square [Contact](0.16x0.16um2) n+ : 87 W p+ : 218 W Hi-R (> 1k Wcm) Std. wafer(p+, ~13 Wcm)

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