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Flip-Flop J-K

Flip-Flop J-K. Flip-Flop J-K. LATCH RS. Flip-Flop J-K. Análise:. 1o. CASO => J = K = 0 => Q = Qn ; Q_inv = Qn_inv => MANTÉM. LATCH RS. R. S. Flip-Flop J-K. Análise:. 2o. CASO => J = 0; K = 1 =>. Q. R. C. Q_inv. S. Flip-Flop J-K. Análise:. Q = 0.

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Flip-Flop J-K

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  1. Flip-Flop J-K

  2. Flip-Flop J-K LATCH RS

  3. Flip-Flop J-K Análise: 1o. CASO => J = K = 0 => Q = Qn ; Q_inv = Qn_inv => MANTÉM LATCH RS R S

  4. Flip-Flop J-K Análise: 2o. CASO => J = 0; K = 1 =>

  5. Q R C Q_inv S Flip-Flop J-K Análise: Q = 0 2o. CASO => J = 0; K = 1 => Q = 0; Q_inv = 1 RESET LATCH RS Se Q = 0 Vcc Q = 0 Q Se Q = 1 R C Q_inv S

  6. Flip-Flop J-K Análise: Vcc Q = 1 3o. CASO => J = 1; K = 0 => Q = 1; Q_inv = 0 Q R C SET Q_inv S Se Q = 0; Q_inv = 1 LATCH RS Q = 1 Q Se Q = 1; Q_inv = 0 R C Q_inv S

  7. Flip-Flop J-K Análise: Vcc Q = 1 4o. CASO => J = 1; K = 1 => Q = (Qn)’; Q R I N V E R T E C Q_inv S Se Q = 0; Q_inv = 1 LATCH RS Vcc Q = 0 Q Se Q = 1; Q_inv = 0 R C Q_inv S

  8. Flip-Flop J-K Tabela de Transição Q J C Q_inv K Símbolo

  9. Descrição Verilog – Flip- Flop JK com reset assíncrono module flip_flop_JK (output reg q, qinv, input clock, j, k, reset_n); always @(posedge clock, negedge reset_n)begin if (~reset_n)begin q <= 0; qinv <= ~q; end else if (k == 1 & j == 0) begin q <= 0; qinv <= ~q; end else if (k == 0 & j == 1)begin q <= 1; qinv <= ~q; end else if (k == 1 & j == 1)begin q <= ~q; qinv <= ~qinv; end end endmodule

  10. Simulação Flip-Flop J-K J = k = 1 RESET Assíncrono Inverte saídas Estado SET Estado RESET

  11. Q J C Q_inv K Q T T C Q_inv Símbolo Flip-Flop tipo T T Tabela de Transição

  12. Descrição Verilog – Flip- Flop T module flip_flop_T (output reg q, input clock, t); always @(posedge clock)begin if (t==1) q <= ~q; end endmodule

  13. Descrição Verilog – Flip- Flop T module flip_flop_T (output reg q, input clock, t); always @(posedge clock)begin if (t==1) q <= ~q; end endmodule Descrição RTL

  14. Descrição Verilog – Flip- Flop T module flip_flop_T (output reg q, input clock, t); always @(posedge clock)begin if (t==1) q <= ~q; end endmodule Descrição RTL Simulação

  15. Descrição Verilog – Flip- Flop T com reset assíncrono module flip_flop_T (output reg q, qinv, input clock, t, reset_n); always @(posedge clock, negedge reset_n)begin if (~reset_n)begin q <= 0; qinv <= ~q; end else if (t == 1) begin q <= ~q; qinv <= q; end end endmodule

  16. Simulação Flip-Flop Tipo T

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