Yield Enhancement - International Technical Working Group ITRS Public Conference in Munich

1. Yield Enhancement - International Technical Working Group ITRS Public Conference in Munich April 12-13, 2005 Lothar Pfitzner, ++49 9131 761 110, lothar.pfitzner@iisb.fraunhofer.de Andreas Nutsch, ++49 9131 761 115, andreas.nutsch@iisb.fraunhofer.de

2. Outline • Chapter Outline • Key Challenges - 2004 (Update) • Organization of the Chapter • Yield Enhancement International Technical Working Group contributors • European YE Forum founded 2004 • Subchapters • Yield Model and Defect Budgets • Defect Detection and Characterization • Yield Learning • Wafer Environment Contamination Control • Conclusion

3. Chapter outline • Scope and topics • improvement from R&D yield level to mature yield • limited to front-end processing • defect detection • yield learning/ramp • Crosscuts • process technologies • facility infrastructure • integrated circuit (IC) design • process integration

4. Key Challenges - 2004 (Update) • The Yield Enhancement community is challenged by the following topics: • Need for high-speed and cost-effective high aspect ratio inspection tools. • Achieve testable and diagnosable designs for integrated circuits. • Data management and test structures for rapid yield learning. • Correlation of impurity level to yield. • Development of parametric sensitive yield models including new materials and considering the high complexity of integration. The understandings of systematic mechanism limited yield are mandatory for achieving historic yield ramps in the future. • Detection of ever-shrinking yield critical defects. • Need for fast and short yield learning cycles at simultaneously increasing process complexity, to achieve historic yield ramps and mature yield levels. • Detection and simultaneous differentiation of multiple killer defect types is necessary at high capture rates and throughput.

5. Organization of the Chapter • Chair: Lothar Pfitzner (IISB) Co-Chair: Dilip Patel (Intel assignee) • Difficult Challenges • Table 107 • Technology Requirements and Potential Solutions • Yield Model and Defect Budget (YMDB) • Chair: Masahiko Ikeno (Renesas) - Japan • Table 108, 109, 110, 111 • Defect Detection and Characterization (DDC) • Chair: Ines Thurner (Infineon) - Europe • Table 112 • Yield Learning (YL) • Chair: Tings Wang (Promos Tech) - Taiwan • Table 113 • Wafer Environment Contamination Control (WECC) – USA • Chair: Kevin Pate (Intel) - USA • Table 114

6. Europe Ines Thurner (Infineon) Lothar Pfitzner (FhG-IISB) Andreas Nutsch (FhG-IISB) Andreas Neuber (M+W Zander) Eric Rouchouze (STM) Dieter Rathei (D R Yield) Japan Masahiko Ikeno (Hitachi-HT) Yuichiro Yamazaki (Toshiba) Eiichi Kawamura (Fujitsu) Fujii Shinji (Matsushita) Sumio Kuwabara (NEC EL) Yosimi Shiramizu (NEC EL) Akira Okamoto (Sony) Seitaa (Sony) Takanori Ozawa (Rohm) Ken Tsugane (Hitachi) Fumio Mizuno (Meisei Univ.) Masakuzu Ichikawa (Univ.of Tokyo) Isao Kojima (AIST) Kazuo Nishihagi (Technos) Yoji Ichiyasu (Hitachi-HT) Yoko Miyazaki (Accretech) United States Kevin Pate (Intel) John Kurowski (IBM) Chris Muller (Purafil) Mike Retersdorf (AMD) Ron Remke (ISMT) Mike McIntyre (AMD) Rick Jarvis (AMD) Ken Tobin (ORNL) Hank Walker (Texas A&M) Ralph Richardson (Air Products) Mark Camenzind (Air Liquide) Joe O’Sullivan (Intel) John DeGenova (TI) Jeff Chapman (IBM) Val Stradzs (Intel) Keith Kerwin (TI) James McAndrew (Air Liquide) Billy Jones (Infineon) Bob McDonald (Metara) Kristen Cavicci (BOCE) Tony Schleisman (Air Liquide) Bart Tillotson (Arch) Tracey Boswell (Sematech) YE ITWG Contributors • Taiwan • Tings Wang (Promos Tech) • Len Mei (Promos Tech) • Steven Ma (Mxic) • Jimmy Tseng (PSC) • CH Chang (SIS) • Chan-Yuan Chen (TSMC) • Jim Huang (UMC) • CS Yang (Winbond) Thank you Very much!

7. European YE Forum Founded 2004 GMM - Task Force: 1.1.1: Production and ManufacturingSub Task: Yield Enhancement • Strengthen European industry by forming a community • Exchange of yield enhancement and defect density methodology • Faster defect and yield learning based on exchange • Generate ideas and innovation • Build sub teams to gain public funding projects • Vision: • Benefits: 16 members: AMD, ATMEL , AMS, ELMOS, IISB, IFX, isiltec, Melexis, Micronas, Philips, Renesas, Bosch, TI, X-Fab, Siltronic, ST

8. Yield Model and Defect Budget • 2004 update highlights • Adjustment of the tolerable particulate contamination due to manufacturing equipment. • future objectives + required 2005 revisions • Evaluation of new defect budget survey. • Discussion on extended yield models adapted to mature yield with special focus on models for systematic yield loss. • Initialize link to WECC.

9. Defect Detection and Characterization • 2004 update highlights • The edge exclusion was aligned between YE, FEP, Litho, and Factory Integration • Update and new calculation of the cost of ownership for defect inspection tools. • future objectives + required 2005 revisions • new table on bevel inspection • revision of existing specifications • cost of ownership model for patterned defect inspection tool • finalize edge exclusion alignment in-between the chapters

10. Yield Learning Volume production • future objectives + required 2005 revisions • Tools for yield analysis – EFA, PFA • Reticle defect inspection and prevention • In-line metrology to yield correlation • DFM and DFT methodology • Adapt tables to volume dependent yield learning (in contrast to time dependant yield learning cycles).

11. Wafer Environment Contamination Control • 2004 update highlights • Point of connection specifications • Add new contamination issues within the table • Future objectives + required 2005 revisions • General • Investigation of deposition models • Address point of use versus point of connection requirements • Wafer environment control and airborne molecular contamination • Focus areas: Litho, Metal & contact (Al, Cu, CoSi2), Gate, Reticle handling & storage, Organics, Dopants, Surface molecular contamination • Measuring methods

12. Wafer Environment Contamination Control • Future objectives + required 2005 revisions (continued) • Ultrapure water • Criticality of anions, ammonia and urea for the process • Specific requirements of immersion lithography • UPW contribution to water spotting • Dissolved oxygen specification relaxation • Speciation of TOC contributors • Process chemicals: • Clarification of critical ions and other specifications by specific chemicals • Identification of newer precursors specification • Particle specification sensitivity • Requirements for slurry particles, planar rinse chems particles & metallics, and plating chems particles  • Bulk and specialty gases • Identify process capabilities • Identify more detailed specialty gas requirements, e.g. dopant levels • Measuring methods for specific contaminants

13. Outlook • Improvement of the yield enhancement chapter • Have a fresh look at the chapter and make necessary changes to reflect current / future needs • Within each section, breakdown concerns from the perspective of impact. In other words some way to prioritize items of concerns • Back to basics – ensure we have enough and necessary players and resources including academia / supplier participation • Need and plan for update as well as alignment of Yield model • Other areas to be considered: • Defect redetection: define requirements to improve redetection capability with improved inspection tool defect location accuracy, software algorithms etc. • Defects of interests: define further requirements to get to defect of interests by improved image processing algorithms and ADC systems to suppress / filter nuisance defects. • Defect characterization: Need for tools to analyze defects smaller than 100nm inline as EDX is reaching its limits.