1 / 34

IEE5011 –Autumn 2013 Memory Systems Duty Cycle Correctors (DCC) In GDDR5 SDRAM

IEE5011 –Autumn 2013 Memory Systems Duty Cycle Correctors (DCC) In GDDR5 SDRAM. Kuang-Yu, Li Department of Electronics Engineering National Chiao Tung University li50916ku@gmail.com. Outline. Introduction Basics DCC and GDDR5 Comparison Analog and Digital DCC All-Digital DCC

gerek
Download Presentation

IEE5011 –Autumn 2013 Memory Systems Duty Cycle Correctors (DCC) In GDDR5 SDRAM

An Image/Link below is provided (as is) to download presentation Download Policy: Content on the Website is provided to you AS IS for your information and personal use and may not be sold / licensed / shared on other websites without getting consent from its author. Content is provided to you AS IS for your information and personal use only. Download presentation by click this link. While downloading, if for some reason you are not able to download a presentation, the publisher may have deleted the file from their server. During download, if you can't get a presentation, the file might be deleted by the publisher.

E N D

Presentation Transcript

  1. IEE5011 –Autumn 2013Memory Systems Duty Cycle Correctors (DCC) In GDDR5 SDRAM Kuang-Yu, Li Department of Electronics Engineering National Chiao Tung University li50916ku@gmail.com

  2. Outline • Introduction • Basics • DCC and GDDR5 • Comparison • Analog and Digital DCC • All-Digital DCC • DCC in GDDR5 • Conclusion

  3. Introduction • GDDR5 • AMD first shipped in 2008 • Sony used in 2013

  4. Basic GDDR5 (1/4)

  5. Basic GDDR5 (2/4) Pre-fetch of 8 Array Bank Grouping New training and tracking New Clocking

  6. Basic GDDR5 (3/4) Data strobe signal (DQS)~>Write data clock(WCK) CKx 1, WCK x2 , Data x4

  7. Basic GDDR5 (4/4) [1]

  8. Basics DCC (1/3) • Why do we need Duty-Cycle-Correctors ? • Improve valid data window • Reduce duty cycle error

  9. Basic DCC (2/3) • Corrects input to 50% duty-cycle • Two functions: • Detect • define 50% boundary • Correct • adjust edge until correct

  10. Basic DCC (3/3) • Design : • Location –on/off path • Integration -embedded or not • Locking time • Operating frequency range • Offset -comes from detector • Implementation -analog or digital • Other (power, area…)

  11. Analog DCC Simple negative feedback

  12. Analog DCC :Detector Integrating Error

  13. Analog DCC :Corrector Cross-coupled differential pair

  14. Digital DCC Simple negative feedback

  15. Digital DCC :Detector • Detection Loop • Time-mutiplexing between clocks • Integrated error and amplified

  16. Digital DCC :Corrector Chargepump :offset adjusting

  17. Analog and Digital Comparison [2] • Digital DCC is preferred! • Power ,range ,function ,supply, mismatch

  18. All-Digital DCC(ADDCC) [3] DLL_out • Wide-range, high resolution • Combined with DLL • Low jitter and fast lock time • Open loop scheme

  19. ADDCC: Timing • Rising of DLL_out and Hclk • Phase error ε,WSG delay α

  20. ADDCC: Cycle Detector • Dual delay line with WSG • Overcoming trade-offs • Small Overhead

  21. Measured Result 69.9% --> 50.6% @440MHz

  22. GDDR5 Clock Distribution P:PLL ,G:Global Driver DQ Pad

  23. DCC in GDDR5 • Wide-range, fast-lock, offset tolerant [5] • Anti-harmonic binary search(ABS) • CML and PLL in clock distribution

  24. DCC in GDDR5 :Adjuster Step: 6ps Range: ±100ps • Between Rx and Driver • Off clock-path –jitter free • 4 phase clock

  25. DCC in GDDR5 :Detector Switch ,ABS circuit, 2 latches, comparator To adder based counter -> Adjuster

  26. DCC in GDDR5 :Detection Methodology iclk vs. qclk and qclk vs. iclkb

  27. DCC in GDDR5 :ABS Circuit • Weighted Delay Cell and range adjuster • Anti-harmonic and wide frequency range

  28. Measured Result Operating frequency and correction range

  29. Measured Result :Locking Time Five input clock ranges

  30. Measured Result :Locking process

  31. Chip Microphotograph 0.0017mm2

  32. DCC in GDDR5 Summary

  33. Conclusion Digital DCC in state of the art DRAM design is necessary and important DCC in GDDR5 with wide-range fast-lock duty-cycle corrector with offset-tolerant capability WCK is up to 3.5GHz to sustain 7Gbps/pin

  34. Reference [1] Kho, R ,et.al, “A 75 nm 7 Gb/s/pin 1 Gb GDDR5 Graphics Memory Device With Bandwidth Improvement Techniques”, IEEE Journal of Solid-State Circuits, vol.45,no.1,pp120 - 133, Jan. 2010 [2] L. Raghavan et.al,  “Architectural Comparison of Analog and Digital Duty Cycle Corrector for High Speed I/O Link,” VLSI Design, pp 270-275,Jan.2010 [3] Dongsuk Shin et.al, “A 7ps-Jitter 0.053mm2 Fast-Lock ADDLL with Wide-Range and High-Resolution All-Digital DCC”, ISSCC,pp184-185, Feb. 2007 [4] Shao-Ku Kaoet.al, “All-Digital Fast-Locked Synchronous Duty-Cycle Corrector” IEEE Transactions on Circuits and Systems ,vol.53,pp 1363 - 1367, Dec. 2006 [5] Dongsuk Shin , Kwang-Jin Na et.al, “Wide-Range Fast-Lock Duty-Cycle Corrector with Offset-Tolerant Duty-Cycle Detection Scheme for 54nm 7Gb/s GDDR5 DRAM Interface,”Symposium on VLSI Circuits Digest of Technical Papers,pp 138-139, June 2009 [6] Kyung Hoon Kim et.al, “A 5.2Gb/p/s GDDR5 SDRAM with CML Clock Distribution Network”, ESSCIRC,pp194 - 197, Sept. 2008

More Related