CompE 460 Real-Time and Embedded Systems

1. CompE 460 Real-Time and Embedded Systems Lecture 5 – Memory Technologies

2. Agenda • Prayer/Thoughts • The CPU-Memory Interface • The Memory Subsystem and Technologies • Volatile Memory • DRAM • SDRAMSRAM • DDR RAM • Non-Volatile Memory • ROM • EEPROM • Flash

3. Memory • What are some different kinds of memory? • Volatile • SRAM: Static Random Access Memory • DRAM: Dynamic Random Access Memory • SDRAM – Synchronous DRAM • DDR SDAM – Dual data rate ram • RDRAM – Rambus DRAM • VideoRAM – Dual Port RAM • Non-Volatile • Read Only Memories • ROM • PROM • EPROM • EEPROM • Flash • MRAM – Magnetic RAM • FRAM – FerroElectric RAM • Phase Change Memory – Based on electrically induced phase change of chalcogenide materials (has both crystaline and non-crystaline states)

4. Memory Cont • In a PC, what do you normally use? • Volatile main memory • Memory Modules • Non-Volatile BIOS • EEPROM/Flash

5. Memory Subsystem Components • Memory subsystems generally consist of multiple chips • Both volatile and non-volatile • And/or multiple chips for each • Depending on system, each chip provides few bytes (e.g., 1­4) per access (like in a PC system), or each provides all bytes for an access (like in most embedded systems) • Bytes from multiple chips are accessed in parallel to fetch words • Memory controller decodes/translates address and control signals

6. Volatile Memory • Forgets memory when power is turned off • Usually volatile is much faster than non-volatile memory • Many types of volatile memory – Usually comes in 2 flavors • Asynchronous • SRAM: Static Random Access Memory • upside: fast and no refresh required • downside: not so dense and not so cheap • often used for caches • DRAM: Dynamic Random Access Memory • upside: very dense (1 transistor per bit) and inexpensive • downside: requires refresh and often not the fastest access times • often used for main memories • Synchronous • SDRAM – Synchronous DRAM – refers to the fact that this DRAM is tied to a common clock with the uproc, so all data is read/write on a particular clock edge (either rising or falling) • DDRAM – Dual data rate ram – data is read/written on each clock edge (both rising and falling)

7. Asynch Mem - Static versus Dynamic RAM • What is a D flip-flop? • Static RAM uses Flipflops for each storage element • What is a capacitor • Dynamic Ram uses capacitors for each storage element D Q CLK

8. Storage Basics • RAM chips don't store whole bytes, but rather they store individual bits in a grid, which you can address one bit at a time

9. address bus CPU Memory data bus Read Write Ready size CPU ­ Async Memory Interface • CPU ­ Asynch Memory Interface usually consists of: • uni­directional address bus • bi­directional data bus • read control line • write control line • ready control line • size (byte, word) control line • Memory access involves a memory bus transaction • read: (1) set address, read and size, (2) copy data when ready is set by memory • write: (1) set address, data, write and size, (2) done when ready is set

10. Storage Basics Cont address bus • Row and Column decoders are simple 1 of X decoders (from CompE 224) • Example: • contains 8 16x1­bit decoders CPU Memory data bus Read Write Ready Size 16x8-bit memory array 0000 1-of-16 decoder 1 0 1 1 0 0 1 0 0001 1 0 0 0 0 0 0 1 address 1111 0 1 0 1 0 0 1 1 D7 D6 D5 D4 D3 D2 D1 D0

11. SRAM Organization and Operations (a) Address lines/decoders to select a row and a column (b) Chip Select (c) Read/Write enable (d) Data in/out

12. 2147H High-Speed 4096x1-bit static RAM 2147H Dout A11-A0 WE CS Din SRAM Memory Timing for Read Accesses • Address and chip select signals are provided tAA before data is available • Outputs reflect new data tRC tAA Address A11-A0 old address new address CS WE high impedance undef Dout Data Valid Address Bus tHz tACS tRC = Read cycle time tAA = Address access time tACS = Chip select access time tHZ = Chip deselections to high­Z out

13. SRAM Memory Timing for Write Accesses • Address and data must be stable tS time-units before write enable signal falls tWC tAA Address A11-A0 old address new address tS CS WE Din old data new data Address Bus tHz tACS 2147H High-Speed 4096X1-bit static RAM 2147H tS = Signal setup time tRC = Read cycle time tAA = Address access time tACS = Chip select access time tHZ = Chip deselections to high­Z out Din A11-A0 WE CS Din

14. DRAM Organization and Operations (a) Address lines/decoders to select a row and a column (b) Chip Select (not shown) (c) Read/Write enable (d) Data in/out (e) Refresh counters

15. DRAM Memory Access • DRAM Memory is arranged in a XY grid pattern of rows and columns (like SRAM) • First, the row address is sent to the memory chip and latched, then the column address is sent in a similar fashion • This row and column-addressing scheme (called multiplexing) allows a large memory address to use fewer pins • BF533 uses this for DRAM memory maps • The charge stored in the chosen memory cell is amplified using the sense amplifier and then routed to the output pin • Read/Write is controlled using the read/write logic

16. How DRAM Works

17. Non-Volatile Memory • ROM – Read Only Memory – come from factory programmed • PROM – Programmable ROM – one time use – programmed with programmer • EPROM – Erasable PROM – can use multiple times – need special eraser to reuse them • EEPROM – Electrically erasable PROM – Typically slow reading/writing – Can be used “in circuit” – generally small memory footprints • Flash – Have to write a block of data – writing is slow, reading fast – will wear out after ~10k to 100k writes

18. Flash Memory

19. Flash Technology - Example • This is an 8 Mbit, 3.0 volt-only Flash memory organized as 1,048,576 bytes or 524,288 words.

20. Flash Technology • Two cautions for flash memory • Flash is usually spec’d as Mb not MB • Reading from flash is same as RAM • Writing to flash requires a sector write

21. Backup

22. DRAM Performance Specs • Important DRAM Performance Considerations • Random access time: time required to read any random single cell • Fast Page Cycle time: time required for page mode access ­­ read/write to memory location on the most recently­accessed page (no need to repeat RAS in this case) • Extended Data Out (EDO): allows setup of next address while current data access is maintained • SDRAM ­ Burst Mode: Synchronous DRAMs use a self­incrementing counter and a mode register to determine the column address sequence after the first memory location accessed on a page ­­ effective for applications that usually require streams of data from one or more pages on the DRAM • Required refresh rate: minimum rate of refreshes