CS35101 Computer Architecture Spring 2006 Week 8

1. CS35101Computer ArchitectureSpring 2006Week 8 P Durand (www.cs.kent.edu/~durand) [Adapted from MJI (www.cse.psu.edu/~mji)] [Adapted from Dave Patterson’s UCB CS152 slides]

3. Head’s Up • This week’s material • MIPS logic and multiply instructions • Reading assignment – PH 3.4 • MIPS ALU design • Reading assignment – PH 3.5 • Reminders • Next week’s material • Building a MIPS datapath • Reading assignment – PH 5.1-5.2

4. zero ovf 1 1 A 32 ALU result 32 B 32 4 m (operation) Review: MIPS Arithmetic Instructions 31 25 20 15 5 0 R-type: op Rs Rt Rd funct I-Type: op Rs Rt Immed 16 • expand immediates to 32 bits before ALU • 10 operations so can encode in 4 bits 0 add 1 addu 2 sub 3 subu 4 and 5 or 6 xor 7 nor a slt b sltu Type op funct ADD 00 100000 ADDU 00 100001 SUB 00 100010 SUBU 00 100011 AND 00 100100 OR 00 100101 XOR 00 100110 NOR 00 100111 Type op funct 00 101000 00 101001 SLT 00 101010 SLTU 00 101011 00 101100

5. carry_in A 1 bit FA S B carry_out Review: A 32-bit Adder/Subtractor add/subt c0=carry_in • Built out of 32 full adders (FAs) A0 1-bit FA S0 B0 c1 A1 1-bit FA S1 B1 c2 A2 1-bit FA S2 B2 c3 . . . S = A xor B xor carry_in carry_out = AB v Acarry_in v Bcarry_in (majority function) c31 A31 1-bit FA S31 B31 c32=carry_out • Small but slow!

6. Minimal Implementation of a Full Adder • Gate library: inverters, 2-input nands, or-and-inverters architecture concurrent_behavior of full_adder is signal t1, t2, t3, t4, t5: std_logic; begin t1 <=not A after 1 ns; t2 <=not cin after 1 ns; t4 <=not((A or cin) and B) after 2 ns; t3 <=not((t1 or t2) and (A or cin)) after 2 ns; t5 <= t3 nand B after 2 ns; S <=not((B or t3) and t5) after 2 ns; cout <=not(t1 or t2) and t4) after 2 ns; end concurrent_behavior; • Can you create the equivalent schematic? Can you determine worst case delay (the worst case timing path through the circuit)?

7. Logic Operations • Logic operations operate on individual bits of the operand. $t2 = 0…0 0000 1101 0000 $t1 = 0…0 0011 1100 0000 and $t0, $t1, $t2 $t0 = or $t0, $t1 $t2 $t0 = xor $t0, $t1, $t2 $t0 = nor $t0, $t1, $t2 $t0 = • How do we expand our FA design to handle the logic operations - and, or, xor, nor ? 0…0 0000 1100 0000 0…0 0011 1101 0000 0…0 0011 0001 0000 1…1 1100 0010 1111

8. add/subt carry_in op A result 1-bit FA B add/subt carry_out A Simple ALU Cell

9. An Alternative ALU Cell s2 s1 s0 carry_in 1-bit FA A result B carry_out

10. The Alternative ALU Cell’s Control Codes

11. Tailoring the ALU to the MIPS ISA • Need to support the set-on-less-than instruction (slt) • remember: slt is an arithmetic instruction • produces a 1 if rs < rt and 0 otherwise • use subtraction: (a - b) < 0 implies a < b • Need to support test for equality (beq) • use subtraction: (a - b) = 0 implies a = b • Need to add the overflow detection hardware

12. less Modifying the ALU Cell for slt add/subt carry_in op A result 1-bit FA B add/subt carry_out

13. A0 result0 B0 + less A1 result1 B1 + 0 less . . . A31 result31 B31 + less 0 set Modifying the ALU for slt • First perform a subtraction • Make the result 1 if the subtraction yields a negative result • Make the result 0 if the subtraction yields a positive result • tie the most significant sum bit (sign bit) to the low order less input

14. op zero . . . add/subt Modifying the ALU for Zero A0 • First perform subtraction • Insert additional logic to detect when all result bits are zero result0 B0 + less A1 result1 B1 + 0 less . . . A31 result31 • Note zero is a 1 when result is all zeros B31 + 0 less set

15. 0 1 1 1 1 0 0 1 1 1 7 1 1 0 0 –4 + 0 0 1 1 3 + 1 0 1 1 – 5 1 0 1 0 0 1 Review: Overflow Detection • Overflow: the result is too large to represent in the number of bits allocated • Overflow occurs when • adding two positives yields a negative • or, adding two negatives gives a positive • or, subtract a negative from a positive gives a negative • or, subtract a positive from a negative gives a positive • On your own: Prove you can detect overflow by: • Carry into MSB xor Carry out of MSB – 6 1 1 7

16. op overflow add/subt Modifying the ALU for Overflow A0 • Modify the most significant cell to determine overflow output setting • Disable overflow bit setting for unsigned arithmetic result0 B0 + less A1 result1 B1 zero + . . . 0 less . . . A31 result31 + B31 0 less set

17. But What about Performance? • Critical path of n-bit ripple-carry adder is n*CP • Design trick – throw hardware at it (Carry Lookahead) CarryIn0 A0 1-bit ALU Result0 B0 CarryOut0 CarryIn1 A1 1-bit ALU Result1 B1 CarryOut1 CarryIn2 A2 1-bit ALU Result2 B2 CarryOut2 CarryIn3 A3 1-bit ALU Result3 B3 CarryOut3

18. 000000 00000 10000 01010 01000 000000 000000 00000 10000 01010 01000 000010 op rs rt rd shamt funct Shift Operations • Also need operations to pack and unpack 8-bit characters into 32-bit words • Shifts move all the bits in a word left or right sll $t2, $s0, 8 #$t2 = $s0 << 8 bits srl $t2, $s0, 8 #$t2 = $s0 >> 8 bits • Such shifts are logical because they fill with zeros

19. 000000 00000 10000 01010 01000 000011 Shift Operations, con’t • An arithmetic shift (sra) maintain the arithmetic correctness of the shifted value (i.e., a number shifted right one bit should be ½ of its original value; a number shifted left should be 2 times its original value) • so sra uses the most significant bit (sign bit) as the bit shifted in • note that there is no need for a sla when using two’s complement number representation sra $t2, $s0, 8 #$t2 = $s0 >> 8 bits • The shift operation is implemented by hardware (usually a barrel shifter) outside the ALU

20. can be formed in parallel and added in parallel for faster multiplication Multiply • Binary multiplication is just a bunch of right shifts and adds n multiplicand multiplier partial product array n double precision product 2n

21. Multiplication • More complicated than addition • accomplished via shifting and addition 0010(multiplicand) x_1011(multiplier) 0010 0010 (partial product 0000 array) 0010 00010110 (product) • Double precision product produced • More time and more area to compute

22. op rsrt rd shamt funct MIPS Multiply Instruction • Multiply produces a double precision product mult $s0, $s1 # hi||lo = $s0 * $s1 • Low-order word of the product is left in processor register lo and the high-order word is left in register hi • Instructions mfhi rd and mflo rd are provided to move the product to (user accessible) registers in the register file • Multiplies are done by fast, dedicated hardware and are much more complex (and slower) than adders • Hardware dividers are even more complex and even slower; ditto for hardware square root

23. 000000 10000 10001 00000 00000 011000 op rs rt rd shamt funct MIPS Multiply Instruction mult $s0, $s1 # hi||lo = $s0 * $s1 • Low-order word of the product is left in processor register lo and the high-order word is left in register hi • Instructions mfhi rd and mflo rd are provided to move the product to (user accessible) registers in the register file

24. Multiplication: Implementation Control Datapath

25. Final Version • Multiplier starts in right half of product What goes here?

26. Division • Division is just a bunch of quotient digit guesses and left shifts and subtracts n n quotient 0 0 0 dividend divisor 0 partial remainder array 0 0 remainder n

27. op rs rt rd shamt funct MIPS Divide Instruction • Divide generates the reminder in hi and the quotient in lo div $s0, $s1 # lo = $s0 / $s1 # hi = $s0 mod $s1 • Instructions mfhi rd and mflo rd are provided to move the quotient and reminder to (user accessible) registers in the register file • As with multiply, divide ignores overflow so software must determine if the quotient is too large. Software must also check the divisor to avoid division by 0.

28. Division: Implementation

29. Division Implementation

30. Integer Division – Example 1

31. Improved Division Hardware Note that the divisor register, the alu, and the quotient register are 32 bits wide. The remainder register is still 64 bits. The quotient register is combined with the right half of the remainder register.

32. Integer Division – Example 3

33. Floating Point (a brief look) • We need a way to represent • numbers with fractions, e.g., 3.1416 • very small numbers, e.g., .000000001 • very large numbers, e.g., 3.15576 ´ 109 • Representation: • sign, exponent, significand: (–1)sign´ significand ´ 2exponent • more bits for significand gives more accuracy • more bits for exponent increases range • IEEE 754 floating point standard: • single precision: 8 bit exponent, 23 bit significand • double precision: 11 bit exponent, 52 bit significand

34. IEEE 754 floating-point standard • Leading “1” bit of significand is implicit • Exponent is “biased” to make sorting easier • all 0s is smallest exponent all 1s is largest • bias of 127 for single precision and 1023 for double precision • summary: (–1)sign´ (1+significand) ´ 2exponent – bias • Example: • decimal: -.75 = - ( ½ + ¼ ) • binary: -.11 = -1.1 x 2-1 • floating point: exponent = 126 = 01111110 • IEEE single precision: 10111111010000000000000000000000

35. Floating Point Complexities • Operations are somewhat more complicated (see text) • In addition to overflow we can have “underflow” • Accuracy can be a big problem • IEEE 754 keeps two extra bits, guard and round • four rounding modes • positive divided by zero yields “infinity” • zero divide by zero yields “not a number” • other complexities • Implementing the standard can be tricky • Not using the standard can be even worse • see text for description of 80x86 and Pentium bug!

36. s E (exponent) F (fraction) 1 bit 8 bits 23 bits Representing Big (and Small) Numbers • What if we want to encode the approx. age of the earth? 4,600,000,000 or 4.6 x 109 or the weight in kg of one a.m.u. (atomic mass unit) 0.0000000000000000000000000166 or 1.6 x 10-27 There is no way we can encode either of the above in a 32-bit integer. • Floating point representation (-1)sign x F x 2E • Still have to fit everything in 32 bits (single precision) • The base (2, not 10) is hardwired in the design of the FPALU • More bits in the fraction (F) or the exponent (E) is a trade-off between precision (accuracy of the number) and range (size of the number)

37. IEEE 754 FP Standard Encoding • Most (all?) computers these days conform to the IEEE 754 floating point standard (-1)sign x (1+F) x 2E-bias • Formats for both single and double precision • F is stored in normalized form where the msb in the fraction is 1 (so there is no need to store it!) – called the hidden bit • To simplify sorting FP numbers, E comes before F in the word and E is represented in excess (biased) notation

38. Floating Point Addition • Addition (and subtraction) (F1  2E1) + (F2  2E2) = F3  2E3 • Step 1: Restore the hidden bit in F1 and in F2 • Step 1: Align fractions by right shifting F2 by E1 - E2 positions (assuming E1  E2) keeping track of (three of) the bits shifted out in a round bit, a guard bit, and a sticky bit • Step 2: Add the resulting F2 to F1 to form F3 • Step 3: Normalize F3 (so it is in the form 1.XXXXX …) • If F1 and F2 have the same sign  F3 [1,4)  1 bit right shift F3 and increment E3 • If F1 and F2 have different signs  F3 may require many left shifts each time decrementing E3 • Step 4: Round F3 and possibly normalize F3 again • Step 5: Rehide the most significant bit of F3 before storing the result

39. Floating point addition

40. MIPS Floating Point Instructions • MIPS has a separate Floating Point Register File ($f0, $f1, …, $f31) (whose registers are used in pairs for double precision values) with special instructions to load to and store from them lwcl $f1,54($s2) #$f1 = Memory[$s2+54] swcl $f1,58($s4) #Memory[$s4+58] = $f1 • And supports IEEE 754 single add.s $f2,$f4,$f6 #$f2 = $f4 + $f6 and double precision operations add.d $f2,$f4,$f6 #$f2||$f3 = $f4||$f5 + $f6||$f7 similarly for sub.s, sub.d, mul.s, mul.d, div.s, div.d

41. MIPS Floating Point Instructions, Con’t • And floating point single precision comparison operations c.x.s $f2,$f4 #if($f2 < $f4) cond=1; else cond=0 where x may be eq, neq, lt, le, gt, ge and branch operations bclt 25 #if(cond==1) go to PC+4+25 bclf 25 #if(cond==0) go to PC+4+25 • And double precision comparison operations c.x.d $f2,$f4 #$f2||$f3 < $f4||$f5 cond=1; else cond=0

42. Control Flow for Floating Point Multiplication

43. Review: MIPS ISA, so far

44. Review: MIPS ISA, so far con’t

45. Review: MIPS ISA, so far con’t