Congestion Driven Placement for VLSI Standard Cell Design

1. Congestion Driven Placement for VLSI Standard Cell Design Shawki Areibi and Zhen Yang School of Engineering, University of Guelph, Ontario, Canada December 2003 (sareibi@uoguelph.ca, zyang@uoguelph.ca) ICM 2003, Cairo

2. Outline Introduction Background Motivation Congestion Optimization Experimental Results Summary & Conclusions ICM 2003, Cairo

3. Introduction • The interconnect has become a critical determiner of circuit performance in the deep sub-micron regime. • Circuit placement is starting to play an important role in today’s high performance chip designs. • In addition to wire length optimization, the issue of reducing excessive congestion in local regions such that the router can finish the routing successfully is becoming another important problem. ICM 2003, Cairo

4. Specification Physical Design Architectural design Partitioning Logic design Placement Circuit design Physical design Routing Test/Fabrication VLSI Design 4

5. Layout Styles Full Custom Semi Custom Cell-Based Array-Based Standard Cell Macro Cell Gate Array FPGA Layout Style 5

6. Standard Cell Layout Style Feedthrough Feature: • Row based layout • Standard cells • Routing channel Standard cell I/O Pads Routing Channel Advantages: • High productivity • More efficient space • Well-suited for automated design 6

7. Objectives Make the size of each component within prescribed ranges Minimize the number of connections between the components. Circuit Layout - Partitioning Task Partition circuit into several sub-circuits. 8

8. In1 In2 1 In1 In3 8 In3 In2 In4 1 5 2 In4 Out1 2 7 6 5 In5 Out1 7 8 In6 3 In7 3 6 4 In5 In7 4 In8 In8 In6 Circuit Layout - Placement Minimize the total estimated wire length of all the nets. Minimize the interconnect congestion. 8

9. Circuit Layout – Global Routing Objectives Minimize the total wire length and critical path delay. 10

10. Determine the location of modules. D L W H R E L Connect the modules inside the boundary of a VLSI chip. O T O Typical Objectives Minimize the chip area Minimize the interconnect delay H E L L O W O R L D Circuit Layout 10

11. 1.0 Delay (ns0 Interconnect delay Gate delay 0.1 1.0um 0.5um 0.25um Minimum Feature Size Why Is Placement Important? The circuit delay, power dissipation and area are dominated by the interconnections. - Circuit Placement becomes very critical in today’s high performance VLSI design. The first phase in the VLSI design that determines the physical layout of a chip. - The quality of the attainable routing is highly determined by the placement. 11

12. Placement Algorithms Constructive Placement Iterative Improvement Simulated Annealing Genetic Placement Cluster Growth Technique Numerical Optimization Force-directed Placement Partitioning Placement Placement Techniques 12

13. Traditional Placement Approach Circuit Generated From Logical Description Initial (global) Placement by Constructive Algorithms Produce a good initial placement in reasonable time Improve (detailed) Placement by Iterative Algorithms Produce a good final placement Valid Coordinates for each cell 13

14. clusters formed from cells in previous level Level n . . . . cluster de-cluster Level 1 de-cluster cluster Level 0 (Flat) Multi-Level Clustering • Bottom-up procedure (clustering) 2. Top-down procedure (de-clustering) initial placement iterative improvement a simple interchange heuristic a high quality solution 14

15. Traditional Methods: Drawbacks • May lead to routing detours around the regions ( i.e. larger routed wire length). • May create an unroutable placement( i.e leads to replacement and repartitioning). • Congestion reduction in placement stage would be more effective. ICM 2003, Cairo

16. Overflow on each edge = Global Bin Global Bin Edge Routing Demand - Routing Supply 0 (otherwise) S Total Overflow = overflow Routing demand = 3 Assume routing supply is 1, overflow = 3 - 1 = 2 . all edges Congestion ICM 2003, Cairo

17. Congestion Reduction Techniques Congestion Reduction Integrated Technique Post-processing Technique Quadratic Placment Simulated Annealing Congestion Reduction During Placment Partitioning Based Placement ICM 2003, Cairo

18. Module Description & Netlist Routing Estimation Initial Placement Congested Region Identification Iterative Improvement Congested Region Expanding Congestion Reduction Congestion Reduction Valid Coordinates for each cell Congestion Optimization ICM 2003, Cairo

19. Based on the probability of having a wire within a global bin covered by the bounding box of net K: bin(0,2) Net K bin(0,0) bin(2,0) Routing Estimation • Bounding Box Routing Estimation. For each yellow bin, the Horizontal Routing Demand of net K is:1/3 Total Horizontal Routing Demand of net K :2 ICM 2003, Cairo

20. S S Cost = Routing Demand +( Overflow)2 Congestion Cost Function Wire length Overflow Total Bounding Box Based Wire length: 4 Horizontal Routing Demand: 2 Vertical Routing Demand: 2 ICM 2003, Cairo

21. Neighborhood bins Bin(i,j) Congested Reg_3 Congested Reg_2 Congested Reg_1 Identifying Congested Regions • A global bin is congested if one of its four global edges is congested. • A maximum number of congested bins in one congested region is set to prevent forming too large congested regions. ICM 2003, Cairo

22. Original Congested Region Expansion Area Congested Region Expansion • For a single congested region, the larger the expansion area is, the better the optimization result can be obtained. • However, the expansions of multiple congested regions may lead to new congested regions. ICM 2003, Cairo

23. Medium Large Small Test Circuits ICM 2003, Cairo

24. Experimental Results • Test Circuit Statistics (for flat approach) ICM 2003, Cairo

25. Congestion Reduction (at flat level) Average Congestion imp: 51% Average Wire length Increase: 3% Average CPU Time Increase: 30% ICM 2003, Cairo

26. Congestion Reduction (at level-3) ICM 2003, Cairo

27. Results Analysis • Incorporating a post processing technique into the hierarchical placement may not be an effective way to reduce the congestion due to the interplay between the wire length placement algorithm and congestion reduction technique. • The wire length minimization should be performed on clustering levels, while the congestion optimization should be only turned on at the flat level. ICM 2003, Cairo

28. Congestion Reduction (after hierarchy) Average Congestion imp:37% Average Wire length Increase: 3% ICM 2003, Cairo

29. Conclusions and Summary • A post-processing congestion reduction technique is implemented and incorporated into the flat and hierarchical placement. • A post-processing technique can reduce the congestion of flat placement largely by 51% on average with a slight increase of wire length. • For hierarchical congestion-driven placement, it seems to be more beneficial to incorporate the congestion reduction phase at the flat level rather than within the levels of hierarchy. • The congestion improvement achieved by performing congestion optimization at the flat level is 37% on average. ICM 2003, Cairo

30. Thank You !

31. E C D E F G A B H A F G H D C B Shorter Wire length Channel Density: 3 (track: 3) Longer Wire length Channel Density: 2 (track: 2) Congestion Driven Placement (channel capacities:2) Unroutable Layout ICM 2003, Cairo