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Evolution-Based Cell Placement: A Heuristic Approach for Minimizing Interconnect Wire Lengths

This study presents an evolution-based approach for cell placement, aiming to minimize interconnect wire lengths on chips by simulating a natural selection process. The algorithm consists of an initial setup phase and a main iterative process, controlled by user parameters like CPU time and wire length. Results are compared to Simulated Annealing, with emphasis on achieving comparable or superior outcomes. High-light of code includes functions for mutation, judgement, and allocation, aiming to optimize cell positions. Outcome representations include numerical data and visual layouts to evaluate solution goodness. Challenges and features are discussed, such as efficient cell placement and enforcing aspect ratios.

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Evolution-Based Cell Placement: A Heuristic Approach for Minimizing Interconnect Wire Lengths

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  1. Evolution-based Standard Cell Placement Jason Woods

  2. Objectives • Implement a heuristic method of simulating an evolutionary process for cell placement • Natural selection • Iterative Improvements • Minimize cell interconnect wire length • “Goodness” • Achieve results comparable or better than Simulated Annealing • Simultaneous removal of large numbers of cells

  3. Methods • Algorithm divided into two main blocks • Initial setup • Main iterative process

  4. Method: Initial Setup • I/O • Input files • Parameters • Chip Floorplanning • Aspect ratio • Average and maximum row lengths • Initial Placement • Precomputations • Approximation of optimal wire length • “Goodness” of the initial placement

  5. Method: Main Iterative Process • Controlled by user parameters (cpu-time, total wire-length, etc.) • Mutation • Introduces randomness • Evaluation • Determines “goodness” current solution • Judgment • “goodness” ratio determines if cell retains position in the next generation • Cells not retaining position are removed and placed in a priority queue

  6. Method: Main Iterative Process Continued • Sorting of Queue • Comparison done by wire lengths • Allocation • Cells in queue are optimally placed in solution

  7. High-Light of Code: Flow Chart

  8. Data Structures Cell Ports Net Connections Rows Slots Layout Cells Nets Rows Code Structure construteInitialSolution() initialPlacement() doPrecomputations() doESP() mutate() evaluate() judge() allocate() PrintResults() High-Light of Code

  9. Result Representation • Numerical • Final wire length • Optimal wire length • “Goodness” of final solution • Visual • Accurate representation of layout • Aspect ratio • Cell widths • Empty slots

  10. Discussion • Challenges • Computation of optimal wire lengths • Efficient placement of allocated cells in queue • Features • Enforcement of an aspect ratio • Net connections to cells not limited to cell parameter • Implementation of 2 part optimal wire length computation • No need to sort queue • Uses of binary search technique for cell enqueuing

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