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Reporting of Standard Cell Placement Results

Reporting of Standard Cell Placement Results. Patrick H. Madden SUNY Binghamton CSD BLAC CAD Group pmadden@cs.binghamton.edu http://vlsicad.cs.binghamton.edu. Thanks.

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Reporting of Standard Cell Placement Results

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  1. Reporting of Standard Cell Placement Results Patrick H. Madden SUNY Binghamton CSD BLAC CAD Group pmadden@cs.binghamton.edu http://vlsicad.cs.binghamton.edu

  2. Thanks Prof. Nael Abu-Ghazaleh, Patrika Agarwal, Dr. Charles Alpert, Andrew E. Caldwell, Prof. Jason Cong, Prof. Shananu Dutt, Dr. Hans Eisenmann, Bill Halpin, Dr. Dennis J.-H. Huang, Prof. Andrew B. Kahng, Prof. George Karypis, Faris Khundakjie, Prof. Cheng-Kok Koh, Prof. John Lillis, Igor L. Markov, Antonis Papadimitriou, Prof. Massoud Pedram, Dr. Bernhard Reis, Prof. Majid Sarrafzadeh, Prof. Carl Sechen, Ryon Smey, Dr. Bill Swartz, Arvind Vidyarthi, Dr Dongmin Xu, Xiaojian Yang, and Mehmet Can YILDIZ

  3. Outline • Problem and Motivation • The Benchmarks • Common Metrics • Reported Results • Summary and Future Work

  4. Standard Cells

  5. Standard Cell Design

  6. Objective • Place cells into rows to minimize wire length, congestion, delay, power, area, ….

  7. MCNC Benchmarks • 10+ years old • Up to 25000 cells • Golem3 benchmark (IBM) has nearly 100K cells

  8. Half Perimeter Wire Length

  9. Motivation:21.882 > 79.9 Yes, that’s correct. Reported results differ widely, and it’s difficult to make comparisons

  10. The Devil is in the Details • How do you measure X? • We do it the same way as everyone else • Well, how exactly is that? • [generally 3 or 4 different responses]

  11. Half Perimeter Wire Length First port defined

  12. Half Perimeter Wire Length Center of cell

  13. Half Perimeter Wire Length Bounding box of pins

  14. Half Perimeter Wire Length Nearest port

  15. Row Spacing

  16. Row Spacing Removal of channel area reduces wire length

  17. Number of Rows Suppose we have an 8x8 mesh…. Primary2: 29[15], 36[14], 28[19][5][7][11][24], 32[8]

  18. Pad Positions

  19. Scaling of Dimensions • Fract, Struct, Biomed, have dimensions scaled by a factor of 2 in TimberWolf based formats • Golem3 has dimensions scaled by a factor of 4

  20. Tool Versions • TimberWolf has many academic and commercial versions • The academic version normally bundled with LAGER does not have the best performance • LAGER generates TW input configured for speed, and not quality

  21. Reported Results:Avqlarge

  22. Scale by 1/4 19.975 21.882 > 79.9? 21.882 79.9 Also, center-to-center, vs. first port, different numbers of rows, pad positions

  23. Summary • There are many unintentional skewed comparisons • No clear winner, for even a metric as simple as HPWL • If we want better placement tools, we should figure out what better means

  24. Nobody cares about HPWL! • Real objective is to minimize delay, power, area, and make sure the chip can be routed (congestion) • 30% difference in length estimate gives a 51% difference in RC delay for the wire…. • But we have to crawl before we walk

  25. Future Work • Some sort of agreement on HPWL and other metrics • New benchmarks for timing, power, routability (and placement competitions?) • Routing – the trouble in placement pales in comparison…

  26. Suggestions • Zero row spacing • Row numbers to allow square core area • Pads at fixed locations • HPWL to use exact pin locations, minimum area bounding box to contain at least one port from each pin • Make placement results available (and tools too, if possible!)

  27. What’s the Best Placer? • Mine, of course… • But seriously, I have no idea (and would be hard pressed to find a pair of tools where I’m confident that one is superior to the other)

  28. How Good are Industry Tools • So good that no one wants to report results for the MCNC benchmarks • Academic tools don’t really consider congestion, delay, power, …. But how far off are we? How much WL do we lose, or should we expect to lose?

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