1 / 51

Universal Test and Operations PHY Interface for ATM (UTOPIA) 1, 2, 3.

Universal Test and Operations PHY Interface for ATM (UTOPIA) 1, 2, 3. S.Y. Yang. The Interface between PHY and ATM. Standardization. UTOPIA Level 1 (1994) UTOPIA Level 2 (1995) UTOPIA Level 3 (1999) UTOPIA Level 4 (Work in Progress) SCI-PHY (1993) SCI-PHY Level 2 (1995).

halden
Download Presentation

Universal Test and Operations PHY Interface for ATM (UTOPIA) 1, 2, 3.

An Image/Link below is provided (as is) to download presentation Download Policy: Content on the Website is provided to you AS IS for your information and personal use and may not be sold / licensed / shared on other websites without getting consent from its author. Content is provided to you AS IS for your information and personal use only. Download presentation by click this link. While downloading, if for some reason you are not able to download a presentation, the publisher may have deleted the file from their server. During download, if you can't get a presentation, the file might be deleted by the publisher.

E N D

Presentation Transcript

  1. Universal Test and Operations PHY Interface for ATM(UTOPIA) 1, 2, 3. S.Y. Yang

  2. The Interface between PHY and ATM.

  3. Standardization • UTOPIA Level 1 (1994) • UTOPIA Level 2 (1995) • UTOPIA Level 3 (1999) • UTOPIA Level 4 (Work in Progress) • SCI-PHY (1993) • SCI-PHY Level 2 (1995)

  4. Before UTOPIA(SUNI)

  5. UTOPIA Level 1. • 8 Bit Data Path • Operating up to 25 MHz • Single PHY device • Interface Bit Rate <= 155 Mbps • Using Sync FIFO for Rate Matching • Octet or Cell Level Handshaking

  6. UTOPIA Level 2. • 16 or 8 Bit Data Path • Operating up to 50 MHz • Multi-PHY Interface • Point-to-Multipoint Physical Topology • Interface Bit Rate <= 622 Mbps • Octet or Cell Level Handshaking

  7. UTOPIA Level 3. • 32 or 16 or 8 Bit Data Path • Operating up to 104 MHz • Interface Bit Rate <= 3.2 Gbps • Point-to-Point Physical Topology • Cell Transfer Burst Mode • Single-edged clocking of data/control/status

  8. SCI-PHY Reference Definition

  9. Transmit Interface TxData[7..0],TxSOC TxEnb* TxFull*/TxClav TxClk Receive Interface RxData[7..0],RxSOC RxEnb* RxEmpty*/RxClav RxClk UTOPIA1: Cell Format & Signal

  10. Octet-Level (1) UTOPIA1: Handshaking of Tx 4 More writes Recognize TxFull* is low

  11. UTOPIA1: Handshaking of Tx • Octet-Level (2) Recognize TxFull* is low

  12. UTOPIA1: Handshaking of Tx Cell-Level (1) Stay asserted until the PHY recognizes that the ATM layer has transmitted payload byte 43 of that cell Recognize TxClav is high

  13. UTOPIA1: Handshaking of Tx Cell-Level (2) PHY can accept another cell from ATM layer.

  14. UTOPIA1: Handshaking of Tx Cell-Level (3) PHY can accept another cell. PHY indicates that it cannot accept another cell from ATM layer

  15. UTOPIA1: Handshaking of Tx Cell-Level (4) Cannot accept another cell from the ATM layer

  16. Octet-Level UTOPIA1: Handshaking of Rx Indicates invalid data.

  17. Cell-Level (1) UTOPIA1: Handshaking of Rx Minimum cycles (2) that is needed to check availability of new cell after deasserting RxEnb* Recognize EOC with internallcounter No new cell is available. New cell is available

  18. UTOPIA1: Handshaking of Rx • Cell-Level (2) ATM layer doesn’t react ATM layer does react

  19. UTOPIA1: Handshaking of Rx • Cell-Level (3)

  20. UTOPIA 1 : Example

  21. UTOPIA 2: Cell Format

  22. UTOPIA 2: MPHY Data Path Operation • Operation with 1 TxClav and 1 RxClav(R) • Cell-Level Handshaking • Poll & Select • Direct Status Indication(O) • Separated TxClav[3..0] & RxClav[3..0] • Common Data Path • Multiplexed Status Polling(O)

  23. Transmit Interface TxFull*/TxClav[0] TxAddr[4..0] TxData[7..0] TxSOC TxEnb* TxData[15..8] TxClav[3..1] TxPrty Receive Interface RxEmpty*/RxClav[0] RxAddr[4..0] RxData[7..0] RxSOC RxEnb* RxData[15..8] RxClav[3..1] RxPrty UTOPIA 2: Signals

  24. Operation with 1 TxClav and 1 RxClav • Transmit Interface (1)

  25. Operation with 1 TxClav and 1 RxClav • Transmit Interface (2)

  26. Operation with 1 TxClav and 1 RxClav • Transmit Interface (3)

  27. Operation with 1 TxClav and 1 RxClav • Receive Interface (1)

  28. Operation with 1 TxClav and 1 RxClav • Receive Interface (2)

  29. Operation with 1 TxClav and 1 RxClav • Receive Interface (3)

  30. Operation with 1 TxClav and 1 RxClav • Receive Interface (4)

  31. Operation with 1 TxClav and 1 RxClav • Receive Interface (4)

  32. Comparison betweenUTOPIA L2 and SCI-PHY L2 • Signal

  33. SCI-PHY L2 : Cell Format

  34. UTOPIA 2 : Example

  35. UTOPIA L3 : 32-bit Mode Cell Format

  36. UTOPIA L3 : 16-bit Mode Cell Format

  37. UTOPIA L3 : 8-bit Mode Cell Format

  38. Transmit Interface TxClav[0] TxEnb* TxSOC TxData[7..0]/TxData[ 15..0]/TxData[31..0] TxClk TxPrty Receive Interface RxClav[0] RxEnb* RxSOC RxData[7..0]/RxData[ 15..0]/RxData[31..0] RxClk RxPrty UTOPIA Level 3: Single PHY Interface Signals

  39. UL3 Single PHY Interface:Transmit Operation(1) 2-clock cycle decode response timing

  40. UL3 Single PHY Interface:Transmit Operation(2)

  41. UL3 Single PHY Interface:Transmit Operation(3)

  42. UL3 Single PHY Interface:Receive Operation(1)

  43. UL3 Single PHY Interface:Receive Operation(2)

  44. UL3 Single PHY Interface:Receive Operation(3)

  45. Transmit Interface TxAddr[n:0] (R) TxClav[3:1] (O) Receive Interface RxAddr[n:0] (R) RxClav[3:1] (O) UL3 MPHY Interface Signals

  46. Multi-PHY Operation with1 TxClav & 1 RxClav • Back-to-back polling

  47. Transmit Operation (1)

  48. Transmit Operation (2)

  49. Receive Operation (1)

  50. Receive Operation (2)

More Related