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8 Bit Arithmetic Logic Unit

8 Bit Arithmetic Logic Unit. Presented by Eric Phan Cong Hoang Paulos Getachew Professor: Dr. David Parent Date: May 7, 2006. Agenda. Abstract Introduction Project Details Results Conclusions. Abstract. Goal is to design a 8-bit ALU performs the following functions: ADDER XOR AND

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8 Bit Arithmetic Logic Unit

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  1. 8 Bit Arithmetic Logic Unit Presented by Eric Phan Cong Hoang Paulos Getachew Professor: Dr. David Parent Date: May 7, 2006

  2. Agenda • Abstract • Introduction • Project Details • Results • Conclusions

  3. Abstract • Goal is to design a 8-bit ALU performs the following functions: • ADDER • XOR • AND • OR

  4. Introduction • ALU is a basic fundamental unit of any computing system. • Understanding how an ALU is designed and how it works is a benefit to building any advanced logic circuits. • Using this knowledge and experience, we can move on to designing more complex integrated circuits.

  5. Project Details • Create schematics and layouts for AOI3333, Kogge-Stone Adder, Flip-Flop, and 4-1Mux by using Cadence tool. • There are 25 D Flip-Flops at the input and 9 at the output. • Using test bench to test schematic. • Create layout of the 8bit ALU. • Run DRC extracted and LVS check to verify the design.

  6. PG Diagram Notation *www-cse.ucsd.edu/classes/wi05/cse246/adderharris.ppt

  7. Kogge-Stone **www-cse.ucsd.edu/classes/wi05/cse246/adderharris.ppt

  8. Block Diagram of 8 Bit ALU

  9. Propagate/Generate Layout & LVS

  10. Black Cell Layout & LVS

  11. D Flip-Flop Layout & LVS

  12. 4-1 MUX Layout & LVS

  13. Logic Verification -- AND

  14. Logic Verification -- OR

  15. Logic Verification -- XOR

  16. Logic Verification -- ADDER

  17. Longest Path Calculations

  18. 8-bit ALU Schematic

  19. 8-bit ALU Layout

  20. 8-bit ALU LVS Report

  21. Transient Analysis

  22. Simulation

  23. Summary • Designed 8 bit ALU with following specifications • Frequency : 200MHz • Area : 774um x 1008µm • Power : 29.28mW • Time Delay: 5ns

  24. Cost Analysis • Time spent on each phase of the project. • Logic design 1 week • Individual schematic 5 days • Integration of schematic blocks 1 week • Layouts 2 week

  25. Lessons Learned • Start early on layout • Use instances

  26. Acknowledgements • Want to thank our classmates for their help • Thanks to Cadence design systems for the VLSI labs • Thanks to Professor David Parent for his guidance.

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