2010 Litho ITRS Update

1. 2010 Litho ITRS Update Lithography iTWG Dec 2010

2. Outline • 2010 • Lithography Potential Solutions • Major Challenges • 2011 • Lithography Potential Solutions • Major Challenges • Some 2011 Update Focus • Summary

3. 2010 Updates

4. July Conference ITRS Litho Working Group

7. Difficult Challenges > / = 16nm

8. Difficult Challenges > / = 16nm

9. Difficult Challenges <16nm

10. Difficult Challenges <16nm

11. Difficult Challenges <16nm

12. Preliminary 2011 Updates

13. December Conference ITRS Litho Working Group

16. Difficult Challenges (2011 - )

17. Preliminary feedback: • No differentiation among different products • No mask cost increase by node • Write time increase • No breakdown on “critical” and “non-critical” • Need to check published data by TSMC and Intel

18. Some 2011 Update Focus • Potential Solutions (long term vs short term) • Number of masks trend • Impact of LWR on EUV mask inspection. • EUV blank surface roughness is not in the spec (actinic and non actinic inspection) • Imprint LER Litho resist spec • DSA – Start a new table OR become part of double patterning • Computational Lithography – Start a new table OR figures • Data Volume for mask and maskless writers update • Max in mask write time (for process control and throughput ) • Mask Grid – 0.5nm (0.125nm 1X) or 0.4nm (0.1nm 1X)?

19. Summary • Lithography solutions for 2010 • 45 nm half-pitch - 193 Immersion Single Exposure for DRAM/MPU • Flash using Double Patterning (Spacer) for 32 nm half-pitch • Lithography solutions for 2013 • 32 nm half-pitch Double patterning or EUV for DRAM/MPU • EUV needed – 16 nm half-pitch for Flash and 22nm DRAM/MPU • Double exposure / patterning requires a complex set of parameters when different exposures are used to define single features • Mask Complexity for Double patterning • Mask Infrastructure for EUV