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2012 ITRS Litho One Pager April 24, 2012. Mark Neisser – SEMATECH Mauro Vasconi – Micron Tatsuo Chijimatsu, Fujitsu Y.C. Ku – TSMC Reiner Garreis -- Zeiss. Updated Challenges. Short term challenges are similar to last update
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2012 ITRSLitho One PagerApril 24, 2012 Mark Neisser – SEMATECH Mauro Vasconi –Micron Tatsuo Chijimatsu, Fujitsu Y.C. Ku – TSMC Reiner Garreis -- Zeiss
Updated Challenges • Short term challenges are similar to last update • Long term challenges add DSA design rules and more EUV complexity
Updated MPU/DRAM Options • Imprint no longer considered an option for 22nm MPU and DRAM, but still option for all 16nm products • DSA + Litho considered more likely than imprint for 16nm and 11nm nodes for MPU, DRAM and flash
Notes • 450nm production use considered unfeasible for 2014 and 2015 • Litho can support proposed accelerated MPU roadmap assuming use of double patterning • ArF immersion plus double patterning for 2013 (27nm half pitch) • EUV with double patterning for 2017 (14nm half pitch) • Will add a DSA table similar to current resist requirements one for the 2013 update