Chapter 12

1. Chapter 12 Test Technology Trends in Nanometer Age

2. What is this Chapter About? • Introduce the test technology roadmap • Focus on a number of difficult challenges and test solutions: • Delay testing, Physical failures and Soft errors, FPGA testing, MEMS testing, High-speed I/O testing, and RF testing • Concluding remarks

3. Section 12.1 Test Technology Roadmap

4. Moore’s Law and Test Challenges • Moore’s law: the number of transistors integrated per square inch will double approximately every 18 months. • To keep track of Moore’s law: die size , feature size , gate delay , interconnect delay • To reduce interconnect delay, interconnects are made taller and taller, and this causes crosstalk noises between adjacent lines due to capacitive and inductive coupling (called signal integrity problem). This is very difficult to test.

5. Moore’s Law and Test Challenges • Power integrity: clock frequency , supply voltage , power supply voltage can drop by L(di/dt). This is very difficult to test. • Process variation: precise control of silicon process is becoming more and more difficult. For example, it is hard to control effective channel length of a transistor. This makes power and delay exhibit large variability. This is hard to detect. • Low-power design faults: low-power design circuits might result in fault models that are difficult to test. For example, drowsy cache design by reducing power supply will cause drowsy faults.

6. Fabrication Capital versus Test Capital

7. International Technology Roadmap for Semiconductors (ITRS) • ITRS identifies technological challenges and needs facing the semiconductor industry over the next 15 years • ITRS test and test equipment near-term challenges [SIA 2004]: • High-speed device interfaces • Highly integrated designs • Reliability screens • Manufacturing test costs • Modeling and simulation

8. International Technology Roadmap for Semiconductors (ITRS) • ITRS test and test equipment long-term challenges [SIA 2004]: • DUT (device under test) and ATE (automatic test equipment) interfaces • Test methodologies • Defect analysis • Failure analysis • Disruptive device technologies

9. International Technology Roadmap for Semiconductors (ITRS) • ITRS design test near-term challenges [SIA 2004]: • Effective speed test with increasing core frequencies and widespread proliferation of multi-GHz serial I/O protocols • Capacity gap between DFT/test generation/fault grading tools/design complexity • Quality and yield impact due to test process diagnostic limitations • Signal integrity testability and new fault models • SOC and SIP test • ITRS design test long-term challenges [SIA 2004]: • Integrated self-testing for heterogeneous SOCs and SIPs • Diagnosis, reliability screens and yield improvement • Fault tolerance and on-line testing

10. Sections 12.2 Delay Testing

11. Why Delay Testing? • Three sources of yield loss • Random defects – causing both logical and timing failures • Systematic failures – causing both logical and timing failures • Parametric variations – more likely causing timing failures Yrandom Ysystematic Yparamtric

12. Fault Models: Path-Delay & Gate-Delay Faults Path-delay fault: • Propagation delay of path exceeds clock interval • # of paths grows exponentially with number of gates • Only consider long paths or a subset of paths • Tests can detect small distributed failures • Tests for longest paths also useful for speed-sorting Gate-delay fault: • A logic model for a defect that delays a rising or a falling transition • Small distributed timing failures could be missed • # of modeled faults is much smaller and manageable

13. Transition Faults & Small Gate-Delay Faults Transition fault (Gross gate-delay fault): • The extra delay caused by the fault is assumed to be large enough to prevent the transition from reaching any PO at the time of observation • Can be tested along any path from fault site to any PO • The test is a vector pair that creates a transition at the fault site and the second vector is a test for the stuck-at fault at the fault site Small gate-delay fault: • Is tested along the longest propagation delay path

14. Off-path inputs Off-path inputs S0 S1 S0 S1 S1 S1 S1 Path Delay Faults - Type of Tests • Single-path-sensitization test: • Guarantee that DUT will fail if and only if the path under test has excessive delay • Fully characterize the timing of the path and is ideal for delay fault diagnosis • All side inputs of gates along the given path must be stable Single-path-sensitization test conditions (for AND gate): Must be stable “1” Must be stable “1” V1 V2 V1 V2 Target path Target path

15. Off-path inputs Off-path inputs S0 / S1 / S0 / S1 / S1 / S1 / S1 / Path Delay Faults - Type of Tests (Cont’d) • Non-robust test : • Test may be invalidated in presence of other path delay faults Non-robust test conditions (for AND gate): Could be either 1 or 0 Could be either 1 or 0 V1 V2 V1 V2 Target path Target path

16. S0 S1 / S0 S1 / Off-path inputs Off-path inputs S1 / S1 / S1 / Path Delay Faults - Type of Tests (Cont’d) • Robust test : • Guarantees DUT will fail if the path under test has excessive delay Robust test conditions (for AND gate): Could be either 1 or 0 Must be stable “1” V1 V2 V1 V2 Target path Target path

17. Application of Delay Tests • Require application of a vector pair to the combinational logic portion and the circuit being clocked at speed input latches output latches Combinational Circuit Input clock output clock Rated clock period Input clock Output clock V1 applied V2 applied Output latched • An arbitrary vector pair may not be applied to a sequential circuit under full-scan, partial-scan or non-scan methodology

18. At-Speed Test • At-speed test means application of test vectors at the rated-clock speed. • Methods of at-speed test: • External, functional test • Functional vectors applied by high-speed testers • At-speed scan test • Built-in self-test (BIST) • Software-based self-test At-speed test does not necessarily guarantee high-quality delay testing unless tests are designed to detect delay faults!

19. MUX Scan Cell Q 1 Q DATA 0 SCAN_IN D-FF MODE_SW CLK Test mode Functional mode Test Mode Functional mode 2cycles L cycles 1cycle L+1 cycles l l l l l l CLK CLK l l l l l l MODE_SW MODE_SW V2 applied V1 applied Response captured V2 applied V1 applied Response captured Applying At-Speed Scan Tests V2 states generated, (A) by one-bit scan shift of V1, or (B) by V1 applied in functional mode. Scan chain length: L Test application scheme (B): Test application scheme (A):

20. Based on test conditions: Based on test application schemes: total path population total path population non-robust testable scan testable robust testable S-P-S testable functional testable Classifications of Paths There are untestable paths even if full-scan is used to deliver tests! But do we really need to test them, if defects/variations on them do NOT degrade circuit performance in functional mode?

21. A Cost-Effective Test Strategy • Use functional vectors • Functional vectors can be applied at-speed and should catch some delay defects. • Functional vectors should be evaluated for transition fault coverage. • Derive and apply tests for undetected transition faults • Derive and apply tests for long path-delay faults

22. Delay Test/Speed Binning Challenges for Nanometer Devices • Delay variability increases due to process, circuit, temperature, power, and noise factors. • No. of critical paths increases due to speed and power saving techniques. • Clock is increasingly susceptible to faults/variations creating test inaccuracy and escapes. • Conventional transition and path delay models and test methodologies are severely challenged!

23. Variability of Path Delay • Noise-induced variability • Coupling cap -- pattern (excitation/propagation)/timing specific • Power grid fluctuation -- pattern specific • Circuit induced -- leakage, charge sharing (pattern specific) • Process-induced variability • Spatial & temporal parametric variability: lot to lot, wafer to wafer, die to die • Limitations in lithography • CMP induced variability • Thermal-induced variability • Power-induced variability Source: TM Mak, Intel

24. More Critical Paths: Slowing Down Non-Critical Paths • Severe power constraint drove power optimization everywhere. • Slowed-down paths + sped-up paths all crowded around required period. • More critical paths make it easier for crosstalk-slowdown to propagate. • Bus coupling effect over local wires may be more likely & frequent.

25. 15/1 e 13/2 b 10/1 g 9/3 c 14/2 f 12/3 d Potential Solution: Go Statistical! • Circuit delays can be modeled as correlated random variables to take various local & global factors into account: • Noise, process variations, pattern dependency, temp. variations, etc. • Global effects can be modeled by correlations factors between delay random variables. Mean/variance of pin-to-pin delay or interconnect delay a

26. Most critical? a 15/1 e 13/2 b 10/1 g 9/3 c 14/2 f 12/3 d Most critical? Notion of Critical Path The most critical path can be different based upon which delay model you have in mind!

27. 15/1 e 13/2 b 10/1 g 9/3 c 14/2 f 12/3 d Critical Path Varies from Chip Instance to Instance P1: a, e, g P2: b, e, g P3: c, f, g P4: d, f, g Suppose 10000 chip instances are produced:

28. Statistical Delay Test & Diagnosis Framework Need to consist of five major components: • Statistical timing analysis • Statistical critical path selection • Selecting statistical long and true paths whose tests maximize the detection of DSM delay defects • Path coverage metric • Estimating the quality of a path set • Generation of high quality tests for target paths • Identifying tests that activate longest delay along the target path • Path delay is highly pattern dependent • Delay fault diagnosis based on statistical timing model

29. (Correlated) cell/interconnect delays Statistical Timing Analyzer • Gate/Cell level • Correlated delay vs. • Cell delay library • Interconnect model • Monte Carlo Based • Automatically determine convergence condition • Static and dynamic • Vector-less or vector-dependent Arrival times (V1V2….) Estimate signal arrival time as random variable

30. Critical Not critical Statistical Critical Paths Arrival time of O • A critical path can be defined as the one with greater than P probability of exceeding a cut-off period T • Adjusting P and T to limit the size of critical path set O I

31. Change of distributions after testing A: Return of testing path A clk Return of testing path B Return of testing path C Considering Path Correlation for Path Selection Output arrival times: 25/3 A overlap 24/3 B C 22/2 After selecting path A, should path B or C be selected?

32. Captured Not captured Considering Path Independence for Path Selection • Defects on selected paths can be captured. • However, a (small) defect falls beyond the selected paths may not be captured. • Even with transition fault tests, path independence can still be an important factor for path selection. Paths selected for test generation

33. Statistical Critical Path Selection • A new method achieving four objectives: • Select statistical long paths • Consider path correlation • Achieve path independence • Eliminate statistical false paths • Results indicating that selecting statistical long paths considering correlation and independence simultaneously: • Achieves higher test quality with the same number of selected paths • Selects fewer paths to achieve same level of test quality *J.-J. Liou, et al., "Experience in Critical Path Selection For Deep Sub-Micron Delay Test and Timing Validation,"ASPDAC2003. *J.-J. Liou, et al., "False-Path Aware Statistical Timing Analysis and Efficient Path Selection for Delay Testing & Timing Validation,"DAC 2002.

34. Section 12.3.1 Signal Integrity and Power Supply Noise

35. Coping with Signal Integrity

36. Signal Integrity • Motivation • Modeling • Test Methodologies • Enhanced BIST • Enhanced Scan

37. New DFTs Cost: Cents/Transistor ITRS Motivation • Test cost will be dominant in this decade [ITRS’01]

38. Result of Technology Scaling Source: [ITRS’01 Roadmap]

39. Shrink of Technology Increase of Frequency Smaller Design Rules Wave-Oriented Phenomena “There are only two kinds of designers: the ones who have signal integrity problems, and the ones who will.” [www.chipcenter.com] Testing for Signal Integrity Physical Defects Process Variations

40. Fatal Problems on First Spin • Overall 61% of new ICs require at least one re-spin [www.deepchip.com]

41. Interconnect Core j Core i The Bottom Line • Signal integrity loss occurs due to process variations, manufacturing defects, the parasitic and coupling C/L. Integrity loss leads to failure. • Signal integrity problem is both design & test issue. A systematic approach for testing is needed.

42. Interconnect Model • Signal integrity problems originate from interconnects. • Distributed RLC model is too complicated.

43. VHthr Vdd VHmin overshoot VLmax ringing Vss VLthr Excessive delay T_SI_R T_SI_F Integrity Loss Model • Excessive delay degrades performance and causes functional error. • Ringing causes functional error. • Overshoot contributes to noise, delay, hot carrier, time-dependent dielectric breakdown, and electromigration.

44. Prior Works • Fault model and test pattern generation • W. Chen, S. Gupta and M. Breuer [ITC98] • M. Cuviello, S. Dey, X. Bai and Y. Zhao [ICCAD99] • A.Attarha, M.Nourani [VTS02] • Self-test methods for testing interconnects • X. Bai, S. Dey and J. Rajski [DAC00] • M. Nourani and A. Attarha [DAC01] [JETTA02] • I. Rayane, J. Medina and M. Nicolaidis [VTS99] • Modified boundary scan • J. Shin, H. Kim and S. Kang [DATE99] • K. Lofstorm [ITC96] • C. Chiang and S. Gupta [VTS97] • S. Yang, C. Papachristou and M. Tabib-Azar [DAC01] • M. Tehranipoor, N. Ahmed, M. Nourani [TCAD04]

45. Method 1: Enhanced BIST • The adverse effects of integrity loss will appear only at the working frequency. • The effects of integrity loss are usually transient and intermittent. • At-speed testing requires high-performance ATEs. • External test of signal integrity is limited due to speed, access and probing difficulties. Output Response Analyzer Test Pattern Generator Interconnect Under Test (IUT) Test Controller

46. On-Chip Noise Detection • The internal Noise Detector (ND) and Skew Detector (SD) cells sample signals and record skew and delay violations. • Our BIST-based methodology can be integrated within conventional BIST environments with 20% to 50% more overhead. T P G R Interconnect Under Test (IUT) ND Cell M I S R SD Cell BIST Controller

47. Noise Detector (ND) Cell • The ND cell detects voltage violations, e.g. overshoot and ringing. signal Core i Core j IUT Signal + noise T6 T3 T4 To read-out circuit c y T7 x T1 T2 Test_mode T5

48. Input: Output: Behavior of the ND Cell • The noise detector (ND) cell shows a hysteresis property and can detect two threshold voltages.

49. Skew Detector (SD) Cell XNOR Sensor Level restorer c To flip-flop Interconnect signal (Signal + Delay) a PDN Inverter 2 TCK TCK b b b Inverter 1 ADR

50. Behavior of the SD Cell ADR Violation