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The Self - Bias PLL I n Standard CMOS

FACULTY OF ELECTRONIC ENGINEERING, UNIVERSITY OF NI Š. LABORATOR Y FOR ELECTRONIC DESIGN AUTOMATION. The Self - Bias PLL I n Standard CMOS. Miljan Nikoli ć Milan Savić Predrag Petković. Introduction. Requirements Phase-Locked Loop Differential Buffer Stage Self-Bias Architecture

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The Self - Bias PLL I n Standard CMOS

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  1. FACULTY OF ELECTRONIC ENGINEERING, UNIVERSITY OF NIŠ LABORATORY FOR ELECTRONIC DESIGN AUTOMATION The Self-Bias PLL In Standard CMOS Miljan Nikolić Milan Savić Predrag Petković

  2. Introduction • Requirements • Phase-Locked Loop • Differential Buffer Stage • Self-Bias Architecture • Circuit Implementation • Conclusion

  3. Reference Frequency of 32768 Hz Output Frequency of 4.194304 Hz Fully integrated Requirements:

  4. Phase-Locked Loop

  5. Differential Buffer Stage

  6. Replica-feedback current source bias generator

  7. Self-Bias Architecture

  8. Loop-Filter

  9. Charge Pump

  10. Simulation Results

  11. Conclusion • Self-Bias in standard CMOS • Simplified Design • Technology and process independance • Area of 0.2 mm2

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