Efficient VLSI Gate Design Through Complementary Logic and Switch Network Integration

1. Chapter 2: VLSI Technology Tahir Muhammad Lecture 2 FPGA-Based System Design

2. Topics • Combinational logic functions. • Static complementary logic gate structures. • Switch logic. • Non-standard gate structures.

3. Combinational logic expressions • Combinational logic: function value is a combination of function arguments. • A logic gate implements a particular logic function. • Both specification (logic equations) and implementation (logic gate networks) are written in Boolean logic.

4. Gate design Why designing gates for logic functions is non-trivial: • may not have logic gates in the libray for all logic expressions; • a logic expression may map into gates that consume a lot of area, delay, or power.

5. Boolean algebra terminology • Function: f = a’b + ab’ • a is a variable; a and a’ are literals. • ab’ is a term. • A function is irredundant if no literal can be removed without changing its truth value.

6. Completeness • A set of functions f1, f2, ... is complete iff every Boolean function can be generated by a combination of the functions. • NAND is a complete set; NOR is a complete set; {AND, OR} is not complete. • Transmission gates are not complete. • If your set of logic gates is not complete, you can’t design arbitrary logic.

7. Static complementary gates • Complementary: have complementary pullup (p-type) and pulldown (n-type) networks. • Static: do not rely on stored charge. • Simple, effective, reliable; hence ubiquitous.

8. Static complementary gate structure Pullup and pulldown networks: VDD pullup network out inputs pulldown network VSS

9. Inverter + out a

10. NAND gate + out b a

11. NOR gate + b a out

12. AOI/OAI gates • AOI = and/or/invert; OAI = or/and/invert. • Implement larger functions. • Pullup and pulldown networks are compact: smaller area, higher speed than NAND/NOR network equivalents. • AOI312: and 3 inputs, and 1 input (dummy), and 2 inputs; or together these terms; then invert.

13. AOI example out = [ab+c]’: invert symbol circuit or and

14. Pullup/pulldown network design • Pullup and pulldown networks are duals. • To design one gate, first design one network, then compute dual to get other network. • Example: design network which pulls down when output should be 0, then find dual to get pullup network.

15. a a dummy c b b c dummy Dual network construction

16. Switch logic • Can implement Boolean formulas as networks of switches. • Can build switches from MOS transistors—transmission gates. • Transmission gates do not amplify but have smaller layouts.

17. Switch logic network a 0 b 1

18. Another switch logic network a r b s

19. Switch-based mux

20. Types of switches

21. Behavior of n-type switch n-type switch has source-drain voltage drop when conducting: • conducts logic 0 perfectly; • introduces threshold drop into logic 1. VDD VDD - Vt VDD

22. n-type switch driving static logic Switch underdrives static gate, but gate restores logic levels. VDD VDD - Vt VDD

23. n-type switch driving switch logic Voltage drop causes next stage to be turned on weakly. VDD VDD - Vt VDD

24. Behavior of complementary switch • Complementary switch products full-supply voltages for both logic 0 and logic 1: • n-type transistor conducts logic 0; • p-type transistor conducts logic 1.

25. Charge sharing • Values are stored at parasitic capacitances on wires:

26. 0 0 0 Charge sharing example 1 1 1 1

27. DCSL gate

28. MTCMOS gate