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EMC for integrated circuits

Seminar at University of Missouri at Rolla Monday 10 th , 2004. EMC for integrated circuits. Etienne SICARD Professor at INSA Toulouse, FRANCE etienne.sicard@insa-tlse.fr. http://www.ic-emc.org. Toulouse: we are Airbus . Toulouse: where I come from . Paris. 400 miles. Bordeaux.

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EMC for integrated circuits

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  1. Seminar at University of Missouri at RollaMonday 10th, 2004 EMC for integrated circuits Etienne SICARD Professor at INSA Toulouse, FRANCE etienne.sicard@insa-tlse.fr http://www.ic-emc.org E. Sicard - EMC for ICs

  2. Toulouse: we are Airbus E. Sicard - EMC for ICs

  3. Toulouse: where I come from Paris 400 miles Bordeaux Grenoble Toulouse Tarbes Aix E. Sicard - EMC for ICs

  4. Contents • The EMC research group • EMC Issues • IC emission • Measurement of emission • IC susceptibility • Measurement of susceptibility • Green chips • EMC models • Future & conclusion E. Sicard - EMC for ICs

  5. 1. The EMC research group www.ic-emc.org E. Sicard - EMC for ICs

  6. European Projects MESDIE, EmcPack L. Courau (B. Vrignon) C. Huet A. Soubeyran (E. Lamoureux, E. Vialardi) PhD thesis (name) French Std Committee UTE Research Contracts Standardization groups IEC, IBIS 1. The EMC research group Research group EMC for ICs IUT Tarbes France J.M Dienot S. Baffreau INSA Toulouse France E. Sicard S. Bendhia ENSA Agadir, Morroco L. Bouhouch, M. Mediouni C. Lochot (C. Labussiere) Alsthom-Pearl (G. Lourdel) Status in May 2004 E. Sicard - EMC for ICs

  7. 2. EMC issues E. Sicard - EMC for ICs

  8. Susceptibility Emission Equipments Mobile phone Personal entrainments Boards Safety systems Component 2. EMC issues Main demand: automotive and aerospace industry E. Sicard - EMC for ICs

  9. Susceptibility level (dBmA) Susceptibility level 50 Between Ics in a board High risk of interference 40 30 Safe interference margin 20 Unsafe margin 10 System in package 0 RF MCU DSP -10 Sum of perturbations -20 Memory ADC DAC -30 -40 Bus control Test f (MHz) 1000 1 10 100 Inside the IC 2. Emc Issues E. Sicard - EMC for ICs

  10. 3. IC Emission E. Sicard - EMC for ICs

  11. FM GSM RF 100 dBµV Not EMC compliant Supplier A 80 60 Supplier B 40 20 Probably EMC compliant Frequency(MHz) 0 10 100 1000 3. IC emission Low parasitic emission is a commercial argument Less decoupling components Lower board quality Less troubles Lower equipment cost New: IC suppliers earn money thanks to EM compliance E. Sicard - EMC for ICs

  12. IDD (0.5mA) ISS (0.5mA) 3. IC emission Basic mechanism for emission: gate current through package inductor VDD VDD Pull Up Pull Up 1 1 Vin 0 0 Output capa Output capa Pull Down Pull Down VSS VSS Microwind E. Sicard - EMC for ICs

  13. 3. IC emission Noise linked to package VDD=2.5V Lead = 10mm 100mA in 1ns CHIP Lead = 10mm VSS=0.0 Noise > 1V E. Sicard - EMC for ICs

  14. di/dt Stronger di/dt Increased Emission problems 3. IC emission Effect of scale down • Current amplitude keeps constant • Faster switching Volt Old process New process Time Current Old process New process Time E. Sicard - EMC for ICs

  15. 2005 2010 3. IC emission Trend: higher noise, wider spectrum Important frequency bands 100 (dBµV) 80 60 64 bit? 32 bit 40 16 bit 20 F(MHz) 0 10MHz 100MHz 1GHz 10GHz Limit 1999 2003 E. Sicard - EMC for ICs

  16. 4. Measurement of Emission E. Sicard - EMC for ICs

  17. 50cm 10x10cm Measure 4. Measurement of Emission TEM method, issued for USA SAE J1752/3 Specific board Shielded box To spectrum analyzer The best radiated mode method (IEC 61967-2) E. Sicard - EMC for ICs

  18. 4. Measurement of Emission GTEM cell : up to 18 GHz Shielding Absorbant Schaffner 250 « Sae » DUT Septum The best candidate for radiated emission 1-10GHz E. Sicard - EMC for ICs

  19. 4. Measurement of Emission German Std VDE UK 767.14 → IEC 61967-4 International Standard Spectrum Analyser IC 1ohm E. Sicard - EMC for ICs

  20. 4. Measurement of Emission Magnetic Probe SAE J1752/2(Japan) → IEC 61967-3 International standard Receiver Probe DUT Other components Can locate high levels of emission, but depends on orientation E. Sicard - EMC for ICs

  21. 4. Measurement of Emission Magnetic Probe (IEC 61967-3) Y axis Amax plot Y axis IC location dBµV X axis Amax Near field scanning helps to improve IC design Near field is a key method for System-in-Package EMC freq X axis E. Sicard - EMC for ICs

  22. 4. Measurement of Emission Summary Radiated DC-1GHz IEC 61967-2 SAE J1752/3 TEM Cell Radiated DC-18GHz GTEM Cell Conducted DC-1GHz UK 767.14 IEC 61967-4 VDE 1 1997 1999 2001 2003 2005 E. Sicard - EMC for ICs

  23. 5. IC Susceptibility E. Sicard - EMC for ICs

  24. Power HF VHF UHF SHF xHF THF 1GW Weather radar Radars Satellites 1MW TV UHF MWave 1KW TV VHF BaseStat Badge Hobby 1W GSM Hobby DECT 1mW Frequency 300 GHz 3 MHz 30 MHz 300 MHz 3 GHz 30 GHz 5. IC Susceptibility Multiple electromagnetic noise sources E. Sicard - EMC for ICs

  25. 5. IC Susceptibility More I/Os, less noise margin Supply (V) 5.0 I/O supply 3.3 2.5 Core supply 1.5 0.7 Technology(m) 0.5µ 0.35µ 0.18µ 90nm 70nm E. Sicard - EMC for ICs

  26. 6. Measurement of Susceptibility E. Sicard - EMC for ICs

  27. DUT 6. Measurement of Susceptibility BCI in CAN Bus (IEC 62132-2) Parasitic current Fault CAN Bus Normal current Microcontroler Coil Inductive coupling to the network Parasitic current injected on the chip Limited to 1GHz E. Sicard - EMC for ICs

  28. 70 60 50 40 30 20 10 0 0 200 400 600 800 1000 1200 1400 1600 6. Measurement of Susceptibility BCI measurement example Current limit I(dBµA) Config 2 Current provoking failure Less sensitive More sensitive Config 1 Frequency limit Frequency (MHz) E. Sicard - EMC for ICs

  29. DUT 6. Measurement of Susceptibility Direct Power Injection « DPI » (IEC 62132-3) High power wave Injection Quite simple to use Very simple to modelize at low frequency Several set-up problems Limited 1 GHz E. Sicard - EMC for ICs

  30. Signal generator Oscilloscope Good signal Coupling Capacitance or Failure signal IEEE Bus 10W Amplifier DUT PC Monitoring 6. Measurement of Susceptibility DPI setup at INSA Device under test Dout Printed Circuit Board E. Sicard - EMC for ICs

  31. 6. Measurement of Susceptibility Workbench Faraday Cage from Philips (WBFC) IEC 62132-5 Common mode methodology Frequency range 150kHz - 1 GHz. Emulates real case equipment. E. Sicard - EMC for ICs

  32. Power Amplifier 6. Measurement of Susceptibility What is available above 1GHz? Most methods limited to 1GHz The GTEM cell could be used as a RF source Its frequency limit is 18GHz (24GHz chamber now exist) Challenger: Reverberating Chamber Not standard available yet fixed E. Sicard - EMC for ICs

  33. 6. Measurement of Susceptibility Summary Conducted DC-400MHz IEC 62132-2 Bulk Current injection Conducted DC-1GHz IEC 62132-3 Direct power injection Conducted DC-1GHz IEC 62132-5 Workbench Faraday Cage 1997 1999 2001 2003 2005 E. Sicard - EMC for ICs

  34. 7. Green Chips E. Sicard - EMC for ICs

  35. 2.5V Exercise2: On-chip 8 bit ADC 100mA in 1ns Adc CHIP Bga Viewer 0 Q2: how many supply pins should be used? 7. Green Chips Rule 1: Reduce the serial inductance Why: because inductance is a major source of resonance 3.3V 50mA in 1ns Exercise 1: target 150mV noise CHIP 0V Q1: how many supply pins should be used? E. Sicard - EMC for ICs

  36. 7. Green Chips • Rule 2: Place VDD and VSS supply as close as possible • Why: • to reduce current loops that provoke magnetic field • to increase decoupling capacitance that reduces fluctuations Added contributions Canceled contributions EM wave current Lead Lead E. Sicard - EMC for ICs Die

  37. VDD VSS 100-1000µm 7. Green Chips Rule 2: Place VDD and VSS supply as close as possible • Supply grid starting 0.35µm • Reduction of parasitic emission Strong current Reduced current Simulation of current flow on a grid E. Sicard - EMC for ICs

  38. 7. Green Chips • Rule 3: Add decoupling capacitance • Why: • to keep the current flow internal • to reduce the supply voltage swing Customer’s specification Parasitic emission (dBµV) 80 70 Volt 60 No decoupling 50 40 30 20 1nF decoupling 10 0 -10 time f (MHz) 1 10 100 1000 E. Sicard - EMC for ICs

  39. 7. Green Chips • Rule 4: Identify & isolate Noisy blocks • Why: • to reduce the injected noise • How • by locating fast signals with strong currents • by separate voltage supply • by substrate isolation • By shunt resistance On-chip capa Shunt resistance Memory array Standardcells Bulk isolation Analog Far fromnoisy blocks Separate supply E. Sicard - EMC for ICs

  40. 7. Green Chips • (Almost a real story) • Warning: • Over current on pin 23 • Ground bounce: voltage drop around 500mV (spec: 50mV) • ADC measured resolution: 6 bits (required 10 bits) • CAN bus erratic problems • Emission 20dB over spec at 100MHz • Send an expert and solve the problems NOW, otherwise we cancel the 10M$ contract New pin assignment Slight on-chip redesign E. Sicard - EMC for ICs

  41. 7. Green Chips CESAME test chip with ST-Microelectronics (CMOS 0.18µm) 6 identical core with various low emission strategies E. Sicard - EMC for ICs

  42. 7. Green Chips CESAME test chip measurements Normal core Confirms the efficiency of low emission design techniques On-chip decap, shunt E. Sicard - EMC for ICs

  43. 8. Models for EMC simulation E. Sicard - EMC for ICs

  44. Architectural Design Version n° Design Entry Design Architect 8. Models for EMC Simulation EMC problems handled at the end of design cycle DESIGN FABRICATION Version n° EMC Measurements Compliance ? NO GO GO + 6 months + $$$$$$$$ E. Sicard - EMC for ICs

  45. Tools Traning Design Guidelines 8. Models for EMC Simulation Dream: find EMC problems before fabrication DESIGN Architectural Design Design Entry Design Architect EMC Simulations Compliance ? Models FABRICATION NO GO EMC compliant GO E. Sicard - EMC for ICs

  46. 8. Models for EMC Simulation The EMC model must include the core and package model • Modelize the core • the internal activity • the supply network • the I/O structure Core Core IC Modelize the Package using R,L,C Package E. Sicard - EMC for ICs

  47. Ib Cd Cb 8. Models for EMC Simulation A standard model for emission: ICEM Lvdd VDD Rvdd Limit of the die VSS Rvss Lvss • ICEM model promoted by UTE (IEC 62014-3) • Used by IC supplier/customer on a non-confidential basis • Available in IBIS website www.eia.org/IBIS or www.ic-emc.org E. Sicard - EMC for ICs

  48. Interpolated Transistor level (Powermill) Gate level Activity (Verilog) Difficult adaptation to usual tools Limited to 1 M devices Simple, not limited Fast & accurate 8. Models for EMC Simulation Modelize the core Physical Transistor level (Spice) Huge simulation Limited to analog blocks 1200 Equivalent Current generator I(mA) 1000 800 600 400 time (ns) E. Sicard - EMC for ICs 200 0 0 20 40 60 80 100 120 140

  49. [Component] ST74FCT16244 [Manufacturer] ST [Package] | variable typ min max | R_pkg 800m 500m L_pkg 6nH 5.5nH C_pkg 8pF 4pF [Pin] signal model R_pin L_pin C_pin 1 /1OE in1 2 1Y1 out1 3 1Y2 out1 4 GND GND 5 1Y3 out1 6 1Y4 out1 8. Models for EMC Simulation Rely on Input Buffer I/O specification (IBIS) for R,L,C and buffer models E. Sicard - EMC for ICs

  50. 8. Models for EMC Simulation Typical flow to compare IC emission simulations with measurements Measurements Simulations E. Sicard - EMC for ICs

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