Digital Integrated Circuits for Communication

1. Digital Integrated Circuits for Communication Class 04

2. Overview

3. Combinational vs. Sequential Logic

4. At every point in time (except during the switching transients) each gate output is connected to either V or V via a low-resistive path. DD ss The outputs of the gates assumeat all timesthevalue of the Boolean function, implemented by the circuit (ignoring, once again, the transient effects during switching periods). This is in contrast to the dynamic circuit class, which relies on temporary storage of signal values on the capacitance of high impedance circuit nodes. Static CMOS Circuit

5. Static CMOS

6. NMOS Transistors in Series/Parallel Connection • Transistors can be thought as a switch controlled by its gate signal • NMOS switch closes when switch control input is high

7. PMOS Transistors in Series/Parallel Connection

8. Complementary CMOS Logic Style Construction (cont.)

9. Example Gate: NAND

10. Example Gate: NOR

11. Example Gate: COMPLEX CMOS GATE

12. Standard Cell Layout Methodology

13. Dynamic CMOS • In static circuits at every point in time (except when switching) the output is connected to either GND or VDD via a low resistance path. • fan-in of n requires 2n (n N-type + n P-type) devices • Dynamic circuits rely on the temporary storage of signal values on the capacitance of high impedance nodes. • requires on n + 2 (n+1 N-type + 1 P-type) transistors

14. Clk Mp ((AB)+C) Out CL A C B Clk Me Dynamic Gate off Clk Mp on 1 Out In1 In2 PDN In3 Clk Me off on Two phase operation Precharge (Clk = 0) Evaluate (Clk = 1)

15. Conditions on Output • Once the output of a dynamic gate is discharged, it cannot be charged again until the next precharge operation. • Inputs to the gate can make at most one transition during evaluation. • Output can be in the high impedance state during and after evaluation (PDN off), state is stored on CL

16. Properties of Dynamic Gates • Overall power dissipation usually higher than static CMOS • no static current path ever exists between VDD and GND (including Psc) • no glitching • higher transition probabilities • extra load on Clk • PDN starts to work as soon as the input signals exceed VTn, so VLT, VIH and VIL equal to VTn • low noise margin (NML) • Needs a precharge/evaluate clock

17. CL Issues in Dynamic Design 1: Charge Leakage CLK Clk Mp Out A Evaluate VOut Clk Me Precharge Leakage sources Dominant component is subthreshold current

18. CL Solution to Charge Leakage Keeper Clk Mp Mkp A Out B Clk Me Same approach as level restorer for pass-transistor logic

19. CL CA CB Issues in Dynamic Design 2: Charge Sharing Charge stored originally on CL is redistributed (shared) over CL and CA leading to reduced robustness Clk Mp Out A B=0 Clk Me

20. Cd=10fF CL=50fF Cb=15fF Cc=15fF Ca=15fF Charge Sharing Example Clk Out A A B B B !B C C Clk

21. CL Issues in Dynamic Design Clock Feedthrough Coupling between Out and Clk input of the precharge device due to the gate to drain capacitance. So voltage of Out can rise above VDD. The fast rising (and falling edges) of the clock couple to Out. Clk Mp Out A B Clk Me

22. Clk In VTn Out1 V Out2 Cascading Dynamic Gates V Clk Clk Mp Mp Out2 Out1 In Clk Clk Me Me t Only 0  1 transitions allowed at inputs!

23. Domino Logic Clk Mp Mkp Clk Mp Out1 Out2 1  1 1  0 0  0 0  1 In1 In4 PDN In2 PDN In5 In3 Clk Me Clk Me

24. Domino Logic • Domino logic is a CMOS-based evolution of the dynamic logic techniques based on either PMOS or NMOS transistors. • It was developed to speed up circuits. • In Dynamic Logic, a problem arises when cascading one gate to the next. • The precharge "1" state of the first gate may cause the second gate to discharge prematurely, before the first gate has reached its correct state. • This uses up the "precharge" of the second gate, which cannot be restored until the next clock cycle, so there is no recovery from this error.

25. Domino Logic • various solutions to the problem of how to cascade dynamic logic gates. • One solution is Domino Logic, which inserts an ordinary static inverter between stages. • While this might seem to defeat the point of dynamic logic, since the inverter has a PFET (one of the main goals of Dynamic Logic is to avoid PFETs where possible, due to speed), • Two reasons it works well. • First, there is no fanout to multiple PFETs. • The dynamic gate connects to exactly one inverter, so the gate is still very fast. • And since the inverter connects to only NFETs in dynamic logic gates, it too is very fast. Second, the PFET in an inverter can be made smaller than in some types of logic gates.

26. Domino Logic • In a domino logic cascade structure consisting of several stages, the evaluation of each stage ripples the next stage evaluation, • similar to a domino falling one after the other. • Once fallen, the node states cannot return to "1" (until the next clock cycle) just as dominos, once fallen, cannot stand up. • The structure is hence called Domino CMOS Logic. • It contrasts with other solutions to the cascade problem in which cascading is interrupted by clocks or other means.

27. Important Domino Logic features: • They have smaller areas than conventional CMOS logic (as does all Dynamic Logic). • Parasitic capacitances are smaller so that higher operating speeds are possible. • Operation is free of glitches as each gate can make only one transition. • Only non-inverting structures are possible because of the presence of inverting buffer. • Charge distribution may be a problem.