EE434 ASIC & Digital Systems

1. EE434ASIC & Digital Systems Jacob Murray School of EECS Washington State University jmurray@eecs.wsu.edu

2. Lecture 9 FPGA fabric architecture concepts Reference: Chapter 3 of the text book

3. Elements of an FPGA fabric • Logic. • Interconnect. • I/O pins. … … IOB IOB IOB LE LE LE interconnect LE LE LE LE LE LE

4. Terminology • Configuration: bits that determine logic function + interconnect • CLB: combinational logic block = logic element (LE) • LUT: Lookup table = SRAM used for truth table • I/O block (IOB): I/O pin + associated logic and electronics

5. Logic element • Programmable: • Input connections • Internal function • Coarser-grained than logic gates • Typically 4 inputs • Generally includes register • May provide specialized logic • E.g., Adder carry chain

6. 0 0 1 0 1 0 0 1 0 0 1 0 1 0 0 1 Example logic element • Lookup table: memory a out b

7. Logic synthesis • How do we break the function into logic elements? • How do we implement an operation within a logic element?

8. Placement • Where do we put each piece of logic in the array of logic elements? … LE LE LE LE LE LE LE LE LE

9. Wiring • An FPGA designer has to rely on pre-designed wiring, unlike a ASIC designer who can design wires as needed to make connections.

10. Programmable wiring • Organized into channels. • Many wires per channel. • Run horizontally and vertically through the chip • Connections between wires made at programmable interconnection points • Must choose: • Channels from source to destination. • Wires within the channels.

11. Programmable wiring paths

12. Choosing a path LE LE

13. Routing problems • Global routing: • Which combination of channels? • Local routing: • Which wire in each channel? • Routing metrics: • Net length • Delay

14. Segmented wiring Length 1 Length 2

15. Offset segments

16. Programming technologies • SRAM • Can be programmed many times • Must be programmed at power-up • Antifuse • Programmed once • Flash • Similar to SRAM but using flash memory

17. SRAM Technique

18. Antifuse • Generally open circuits, low resistance when programmed • Modified CMOS technology

19. I/O • Fundamental selection: input, output, tristate (high impedance)? • Additional features: • Register • Voltage levels

20. Configuration • Must set control bits for: • LE • Interconnect • I/O blocks • Usually configured off-line • Separate burn-in step (antifuse) • At power-up (SRAM)

21. LUT-based logic element n inputs 1 Lookup table configuration bits out Can multiplex at output or address at input

22. Configuration vs. programming • FPGA configuration: • Bits stay at the device they program. • A configuration bit controls a switch or a logic bit. • CPU programming: • Instructions are fetched from a memory. • Instructions select complex operations. memory CPU add r1, r2 IR add r1, r2

23. Reconfiguration • Some FPGAs are designed for fast configuration. • A few clock cycles, not thousands of clock cycles • Allows hardware to be changed on-the-fly

24. Evaluation of SRAM-based LUT • N-input LUT can handle function of 2N inputs. • All logic functions take the same amount of space. • All functions have the same delay. • SRAM is larger than static gate equivalent of function. • Burns power at idle. • Want to selectively add register to LE.

25. D Q Registers in logic elements • Register may be selected into the circuit: Configuration bit LUT LE out

26. Other LE features • Multiple logic functions in an LE. • Addition logic: • carry chain • Partitioned lookup tables

27. Xilinx Spartan-II CLB • Each CLB has two identical slices. • Slice has two logic cells: • LUT • Carry logic • Registers

29. Spartan-II CLB details • Each lookup table can be used as a 16-bit synchronous RAM or 16-bit shift register. • Arithmetic logic includes an XOR gate. • Each slice includes a mux to combine the results of the two function generators in the slice. • Register can be configured as DFF or latch. • Has tristate drivers (BUFTs) for on-chip busses.

30. Spartan-II CLB operation • Arithmetic: • Carry block includes XOR gate • Use LUT for carry, XOR for sum • Registers can be FF/latch; clock and clock enable • Includes tristate output for on-chip bus

31. Altera APEX II logic element • Each logic array block has 10 logic elements. • Logic elements share some logic.

33. Apex II LE modes • Modes of operation: • Normal • Arithmetic • Counter

34. APEX-II LE normal mode

35. APEX-II LE arithmetic mode

36. APEX-II LE counter mode