EE434 ASIC & Digital Systems

1. EE434ASIC & Digital Systems Jacob Murray School of EECS Washington State University jmurray@eecs.wsu.edu

2. Digital Design with Verilog Lecture 18

3. Modules

4. Port Definition module adder_implicit (result, carry, r1, r2, c_i); //input port declarations// input [3:0] r1 ; input [3:0] r2 ; input c,_i ; //output port declarations// output [3:0] result ; output carry ; // … endmodule

5. Ports

6. wire • A wire data type in a Verilog description represents the physical wires in a circuit • A wire does not store its value. It must be driven in one of two ways: • By connecting the wire to the output of a gate or module • By assigning a value to the wire in a continuous assignment wire a; wire [2:0] b; • An input is of type wire by default and is governed by the syntax of wire.

7. reg A reg representsa variable (usually register) in Verilog

8. Continuous Assignments Driving a value onto a wire

9. Module Instantiations A module instantiation consists of the name of the module (module_name) followed by one or more instantiations.

10. Named & Positional Notation • SEQ_1 is instantiated by the use of positional notation, as follows: • Signal D0 is connected to port BUS0 of module SEQ. • Signal D1 is connected to port BUS1. • Signal OUT0 is connected to port OUT. • SEQ_2 is instantiated by the use of named notation, as follows: • Signal OUT1 is connected to port OUT of the module SEQ. • Signal D3 is connected to port BUS1. • Signal D2 is connected to port BUS0.

11. Bitwise Operators module gates (input [3:0] a, b, output [3:0] y1, y2, y3, y4, y5); assign y1 = a & b ; //AND compare with && assign y2 = a | b ; //OR compare with || assign y3 = a ^ b ; //XOR assign y4 = ~(a & b) ; //NAND assign y5 = ~(a | b); //NOR endmodule

12. Reduction Operators module and5 (input [4:0] a, output y); assign y = &a; endmodule assign parity = ^in; assign all_ones = ∈

13. Shift Operators A shift operator takes two operands and shifts the value of the first operand right or left by the number of bits given by the second operand.

14. Conditional Operator module mux2 (input [3:0] d0, d1, input s, output [3:0] y); assign y = s ? d1 : d0; endmodule

15. Nested Conditional Operator

16. Concatenation Operator

17. Internal Signals modulefulladder (input a, b, c_in, output s, c_out ); wire prop; assign prop = a ^ b; assign s = prop ^ c_in; assignc_out = (a & b) | (c_in & (a | b)); Alternatively, assignc_out = a & b | c_in & (a | b);

18. Tristates module tristate (input [3:0] a, input en, output [3:0] y); assign y = en ? A : 4 ’ bz ; endmodule

19. Supply0 & Supply1 • The supply0 and supply1 data types define wires tied to logic 0 (ground) and logic 1 (power). • Using supply0 and supply1 is the same as declaring a wire and assigning a 0 or a 1 to it. supply0 gnd; supply1 power;

20. Arrays reg data [7:0]; // 8 1-bit data elements integer [3:0] out [31:0]; // 32 4-bit output elements Memories are simple array of registers (regvectors) // memory mem16_1024 is 1K of 16 bit elements reg [15:0] mem16_1024 [1023:0]; // referencing (16-bit) word 489 of mem16_1024 readout <= mem16_1024[489];

21. if…else

22. Nested if…else