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CLASS GRADING HOMEWORKS PROJECTS REVIEW OF DIGITAL LOGIC. Digital Design using VHDL and Verilog. Marek Perkowski Department of Electrical and Computer Engineering Portland State University. Introduction. Administration About Review RASSP Program Why VHDL?
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CLASS • GRADING • HOMEWORKS • PROJECTS • REVIEW OF DIGITAL LOGIC
Digital Design using VHDL and Verilog Marek Perkowski Department of Electrical and Computer Engineering Portland State University
Introduction Administration About Review RASSP Program Why VHDL? Flip-Flops (see ECE 271 class slides) Shift Registers Generalized Register Pipelined Sorter
Administration • Instructor: Prof. Marek A. Perkowski • Course Information • My home page http://ee.pdx.edu/~mperkows • Computer Engineering web site • http://ece.pdx.edu
Administrative • Office • FAB room 160-05 • Office Hours • Fridays 6 pm - 10 pm - meetings in FAB, room 150 • Other Times by Appointment • Office Phone • (503)725-5411 (Answering Machine)
Administrative • Email • mperkows@ee.pdx.edu • Students with Disabilities • If you need special assistance, please inform me soon so that we can work something out. • There is a milestone chart available on the class web site.
Grading • HW 35% • Assignments are on the web, may be changed. If changed, I will inform you. Usually these are mini-projects. You may be asked to present them in class. • Final Project 65% • You will present it in class • No exams
Grading • Attendance at Lecture • Not graded, but recommended. • Attendance at Friday meetings not graded, come if you can. • Makeup Exams • Makeup homeworks or exams are not given. • Project should be completed before end of the class
More details on this year class • There are two homeworks – 35% • Project is 65% • No exam, no midterms. • You will need to make a good quality presentation of project. • I may ask you to present your homework as well. • A homework or both homework may be part of your final project. • A group can have from one to three people. • Each team member is responsible for part of coding – no person can have a grade in this class if he/she has not done coding and simulation.
More details on this year class • Every team has to do simulation using Modelsim. • Most of you have free CAD software, other should contact CATs or Philip or me. • Good and complete software comes also with Wakerly book. • A more ambitious project involves compiling your simulated design to FPGA – you should have your own FPGA (around 250 dollars). • A more ambitious project involves Veloce Emulation. • Additional one credit or more are possible related to this class. • There are chapters of our book available • http://web.cecs.pdx.edu/~mperkows/CLASS_VELOCE_2011/index.html • More chapters will be added soon. • This is very much related to projects from the class.
Homeworks • Homeworks Require Use of VHDL • Always you have to simulate the circuit • You may be asked to synthesize it also. • Mentor Graphics Tools • contact support (cat) people • use any lab that is available. Work at home. • use addpkg • We use Modelsim for simulation and LeonardoSpectrum for synthesis. Synthesis is mandatory for the project.
Slides • My slides are based on at least 5 books, slides from Internet and my industrial experience, on top of teaching this class since 1989. You can learn all you need if you read slides in detail. • Not always I will cover all slides in class. In such case you have to complete reading slides for this week at home. • You can learn a lot from previous homeworks and projects that are posted.
Required and Additional Textbooks • Required and recommended • VHDL and FPLDs. Zoran Salcic. CD ROM included. Kluwer Academic Publishers • see my web page • Additional • The Designer’s Guide to VHDL • Peter J. Ashenden • Morgan-Kaufman • ISBN 1-55860-270-4 (paperback) • LOC TK7888.3.A863 • Dewey Decimal 621.39’2--dc20 • 1996
Resources • IEEE Standard 1076-1993 • find using search engines on WWW • Use my WWW Page resources, too much to digest. • IEEE Interactive VHDL Tutorial • On-line on Computer Engineering Home page • http://cpe.gmu.edu • password protected
Resources • Our Book • Cypress Semiconductor (Warp release 5.x) • PC-based • $99 with textbook • Oriented towards Their PLD & FPGA devices • VHDL Subset simulator • Xilinx FPGA • Student edition • Schematic, FSM, VHDL
Honor Code • You Are Encouraged to Collaborate With Other Students in Projects. • Final VHDL code for each Homework should be done by yourself. • In Final Project, each file should have at the top student name of the student responsible for this part of code.
Remind the class…. • Your webpage • List of your names with interests and experiences. Previous design projects that you have done. • Any experience in robotics? • Any experience in pipelined and systolic processors? • Any experience with image processing? • Previous VHDL or Verilog projects. • C++ experience • Other languages like LISP, Prolog, Basic, etc. • I will intentionally repeat the most important parts of material or ideas. I believe in real understanding of material by students and good understanding of fundamentals is most important for me. • You have to understand the combinational logic, flip-flops, registers, state diagrams, pipelining, ALU, etc.
Homework 1 • Simple Satisfiability Machine • Simple Petric Function Oracle based machine • Any type of Sorter • Fibonacci sequence generator • GCD • LCM • Any other controller from CU and DP. • Any other oracle, SEND+MORE=MONEY, graph coloring, etc. These are just examples, more projects will be added, you can propose your own project.
High Level System DesignPossible VHDL Projects for Spring 2012 Marek Perkowski
Oracle Based Homeworks and Projects • SAT solvers • Petrick Function and similar decision function solvers • Graph Coloring Optimizing Architecture • Image Matching by maximum clique. • (reserved for Alan Cheng) General Solver for Cryptography. Problems like: SEND+MORE=MONEY. • Universal Sudoku Machine • Hardware solvers for Generalizations of Sudoku
Projects for year 2012 Oracles • Graph Coloring (optimized) • FPRM learning • Logic Puzzles • Error Correcting codes design • Traveling Salesman • Any other oracles with practical use These are just examples, more projects will be added, you can propose your own project.
Robotics Related VHDL projects • State Machine controller that learns from examples. • Evolutionary algorithms (such as Genetic Algorithm) in hardware • Backtracking search optimizer for mazes. • Early Vision system for a robot. • Camera interface. • Microphone interface. • Interfaces for motion control for servo motors, DC motors and Stepper Motors. • Subsumption architecture. • Inverse kinematics solver. • General purpose robotic FSM controller with timers, stacks and decision modules. • Probabilistic State Machine and Hidden Markov Model for a robot. • Converter of human speech to robot head/neck motion.
Projects for year 2012 Robotics • SpeechRecognition for a robot (new) • Rough Set Machine (continuation - Torrey Lewis) • Convolutional Image Processor (continuation) • Controller of a Robot (new) • Evolvable Hardware (new) These are just examples, more projects will be added, you can propose your own project.
Projects for year 2012 Cellular Automata and Robotics • Mandelbrot Set with quaternions and octonions • Robot Vision with morphological algebras • Galois Field Arithmetics for robot vision • Neural Net for a robot • PID controller for a robot • Sum of Product minimization for a robot • Decision trees in hardware for robot • Car model control • Logic Decomposition These are just examples, more projects will be added, you can propose your own project.
Cellular Automata • Variants of Game of Life • Biosystems simulation • Quantum Physics simulation • Firing Squad architecture • Dining Philosophers and applications.
Projects for year 2012 Cellular Automata and Robotics • Hidden Markov Model • Kalman Filter for robot • Particle Filter for robot obstacle avoidance • Genetic Algorithm in hardware These are just examples, more projects will be added, you can propose your own project.
Computer architecture • Computer Graphics • LISP machine • Prolog Machine • General Hardware Search Solver • Contents Addressable Memory architecture with internal processing – for tautology and similar problems.
Advanced Digital Design, Modal Logic • Muddy Children and Modal/Temporal Logic. • Narrow Bridge Problem (is this CA?) • Your own invention related to Modal or Temporal Logic.
Pipelined and Systolic Processors • Sorters • Sorters/absorbers • Cube calculus data flow machines.
Projects for year 2012 Transforms • Hough Transforms • Radon Transforms • Fast Fourier Transform • Hadamard • Haar • Adding • Arithmetic • Gabor These are just examples, more projects will be added, you can propose your own project.
Review • Mealy and Moore • Registered Output • Rabin-Scott
Function Minterms and Maxterms Discuss generator of all functions of certain type, use MUX as example
