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AC7 CO Chipset Increasing Services and Reducing Total Cost of Ownership

AC7 CO Chipset Increasing Services and Reducing Total Cost of Ownership. DSL Market Requirements. Reduced Costs More subscribers per chipset /chassis. New Features Support for new standards. Backward Compatibility Support for legacy standards. Interoperability

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AC7 CO Chipset Increasing Services and Reducing Total Cost of Ownership

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  1. AC7 CO ChipsetIncreasing Services and Reducing Total Cost of Ownership

  2. DSL Market Requirements Reduced Costs More subscribers per chipset /chassis New Features Support for new standards Backward Compatibility Support for legacy standards Interoperability High-performance with all CPEs

  3. AC7 Answers Needs of OEMs and Operators Reduced Costs Simplified AC7 design reduces total cost of ownership (TCO) for operators’ ADSL systems & networks New Features Operators can seamlessly support ADSL2, ADSL2+, Annex L and READSL Backward Compatibility AC7 supports all legacy ADSL standards Interoperability AC7 offers the industry’s strongest interoperability performance

  4. AC7: New Features, New Integration”Extending True Density Leadership” Dual AFE on Silicon Dual AFE on Silicon Dual AFE on Silicon Dual AFE on Silicon Dual AFE on Silicon Dual AFE on Silicon Dual AFE on Silicon Dual AFE on Silicon AC7 Chipset Parameters • Power: <750mW • Area: 0.9 sq. inches/port • BOM: <$0.85/port • 23 Discretes • Interfaces: • Utopia 2 • POS (packet over Sonet) PHY • High Speed Serial (LVDS) • PCM (pulse code modulation) • Management • Standards: • ADSL2, ADSL2+, READSL • T1.413i2, ETSI, G.DMT • Annex A, B, C, I, J, L PCM 16 Port Multi-Service DSL Transceiver LVDS Mgmt Utopia 2 / POS-PHY

  5. CO: Infrastructure Product Integration 16 Port Example Shrink Shrink AC7 1 chipset 9 chips 368 discretes <750mW AC5 2 chipsets 20 chips 752 discretes 1.3W AC6 2 chipsets 12 chips 624 discretes 920mW ADSL CO Bill of Material Digital Xcvr (x8) 0.15μ Digital Xcvr (x8) 0.15μ Digital Xcvr (x16) 0.13μ Digital Xcvr (x8) 0.15μ Digital Xcvr (x8) 0.15μ Mixed Signal Codec (x8) Mixed Signal Codec (x8) Single-Chip DSL Modem Complete AFE on a Chip (x2) Mixed Signal Codec (x8) Mixed Signal Codec (x8) Line Xcvr (x1) Dual Line Xcvr (x2) Line Xcvr (x1) 22 Discretes 38 Discretes 42 Discretes Transformer (x1) Transformer (x1) Transformer (x1)

  6. All High Density CO Chipsets are Not the Same MCM-based Solutions Legacy Solutions Memory Memory Digital XCVRx8 Codec x8 Driver, Codec, Hybrid x2 Digital XCVR, Memory, Codec x16 Digital XCVR x12 Codec x12 Driverx2 Driverx1 Digital XCVRx8 Codec x8 Hybrid Hybrid Analog Signal Traces Analog Signal Traces 23 Components External Hybrid External Hybrid 40-50 Components/port 40-50 Components/port • Integrated 2-chip Solution • Analog Signal Trace Elimination • Integrated Programmable Hybrid • Integrated Memory • Multi-chip Module – a single package butnot one piece of silicon • External Memory • Single Channel Driver • Older Classic Three Chip Architecture • Less Silicon/Package Integration • External Memory

  7. Extending True DensityCompetitive Comparison Die Count Chip Count Chip and Die Count Comparisons (48 Port Linecard) TI AC7 Density Delta Company Die Chip ADI -56% -48% STM -33% -33% GSPN -33% -25% INFN -25% -25% CTLM/BRCM -16% -16% 60 50 40 30 20 61 52 40 40 40 36 36 36 Higher Integration 32 32 27 27 Means Lower System Costs 27 • Fewer PCB Layers • Decreased Trace Density • Easier Board Routing • Fewer Components to Manage ADI* x16/x0/x1 STM x12/x4/x2 GSPN G24* x24/x8/x2 INFN x8/x4/x2 TI AC7 x16/x0/x2 CTLM / BRCM x12/x12/x2 Digital Chip / Codec Chip / Driver Chip * Requires external memory

  8. Making DSL Networks Simple“Multi Standard/Multi-Service” Subscriber #1 READSL Ready ADSL2+ Ready Subscriber #2 Subscriber #3 Subscriber #4 6kft (1.8km) 9kft (2.75km) Subscriber #5 12kft (3.6km) 15kft (4.6km) • Before AC7 • Subscriber #1 • Moderate User • Globespan CPE • G.dmt With AC7 • Fully Interoperable • No CPE Change Costs • No Operational Expenses • Subscriber #2 • Moderate User • Alcatel CPE • T1.413i2 • Fully Interoperable • No CPE Change Cost • ADSL2+ Capable • Revenue Potential Increases • Subscriber #3 • Not Served • READSL Ready • Revenue Potential Increases • Subscriber #4 • Heavy User • TI AR7 CPE • ADSL2 • ADSL2+ Ready • Soft “Up-Sell” Market Created • Revenue Potential Increases • Subscriber #5 • Light User • Alcatel CPE • G.dmt • Fully Interoperable • No CPE Change Costs • No Operational Expenses 15kft is the typical operator standard serving area. With AC7, operators can offer ADSL2+ and READSL plus all users have enhanced upstream capabilities.

  9. Total Cost of Ownership AdvantageAddressing the DSL Investment Chain AC7 Advantage AC7 Advantage OEM Expenses Service Provider Expenses H/W Development Capital • System costs • Linecard costs • Separate service cards • Multi-service chipsets • One board for world market • Trace count reductions • Most integrated chipset • Lowest system cost enabled • Multi-service linecards • Multiple designs • Board re-spins • CAD resources S/W Development Provisioning • Managing Multiple API’s • Common API w/previous • & future chipsets • Broad interoperability testing • Multi-standard support • Truck rolls • Interop problems Testing Operational • Advanced analog built in self test • Board debug • Lowest power consumption • Network level electricity draw Operational Maintenance • ADSL2: DELT • Interoperability stability • Fewer linecard potential failure points • Fault isolation • Modem stability • Failure rates • 33% reduction in chip count • 23 passives/port • Purchasing • Inspection • Inventory • Assembly

  10. Offering Superior End-to-End Interoperability Interoperability is the fundamental requirement for all operators worldwide Over 225 CPEs and 30+ DSLAMs can be tested against in TI’s DSL interoperability lab TI’s world-class interoperability lab delivers: • Automated testing with latest deployed equipment • Database for test data storage and comparisons • Operator reports, TI SW release interoperability reports TI’s interop lab facility shortens manufacturer and operator qualification cycle

  11. AC7: Summary Simplified Design Reduces Total Cost of Ownership ADSL, ADSL2, ADSL2+, Annex L, READSL Support Backward Compatibility with Legacy CPEs Industry Leading Interoperability 16 Port Multi-Service/Multi-Standard Chipset Integration on Silicon -- True 2-Chip Solution <750mW/port, 23 Discretes/port

  12. Backup

  13. AC7 versus Broadcom (w/ Intersil) Board Complexity Comparison (48 Port Example) Analog Signal Trace Elimination (PCB, Debug) Advantage TI Broadcom TI AC7 32- Chip Count -27 (Inventory, Manufacturing) Advantage TI Hybrid Hybrid Driver x2 Driver x2 Hybrid Hybrid Driver x2 Driver x2 Hybrid Hybrid Hybrid Hybrid Hybrid Hybrid DSP x16 Codec x12 Driver x2 Driver x2 Hybrid Hybrid DSP x12 Codec x12 Driver x2 Driver x2 Hybrid Hybrid Hybrid Hybrid Hybrid Hybrid Driver x2 Driver x2 Hybrid Hybrid Driver x2 Driver x2 Hybrid Hybrid Hybrid Hybrid Integrated Hybrid (BOM $, Manufacturing) Advantage TI Hybrid Hybrid Driver x2 Driver x2 Hybrid Hybrid Driver x2 Driver x2 Hybrid Hybrid Hybrid Hybrid DSP x12 Codec x12 DSP x12 Codec x12 Hybrid Hybrid Driver x2 Driver x2 Hybrid Hybrid Driver x2 Driver x2 Hybrid Hybrid Hybrid Hybrid Hybrid Hybrid Driver x2 Driver x2 Programmable Hybrid (Performance) Advantage TI Hybrid Hybrid Driver x2 Driver x2 Hybrid Hybrid Hybrid Hybrid Hybrid Hybrid Driver x2 Driver x2 Hybrid Hybrid Driver x2 Driver x2 DSP x16 Codec x12 Hybrid Hybrid DSP x12 Codec x12 Hybrid Hybrid Hybrid Hybrid Driver x2 Driver x2 Hybrid Hybrid Driver x2 Driver x2 Hybrid Hybrid Codec Integration (PCB, Inventory) Advantage TI Hybrid Hybrid Hybrid Hybrid Driver x2 Driver x2 Hybrid Hybrid Driver x2 Driver x2 Hybrid Hybrid Hybrid Hybrid DSP x16 Codec x12 Hybrid Hybrid Driver x2 Driver x2 Hybrid Hybrid Driver x2 Driver x2 Hybrid Hybrid DSP x12 Codec x12 Hybrid Hybrid Hybrid Hybrid Driver x2 Driver x2 Hybrid Hybrid Driver x2 Driver x2 Hybrid Hybrid Hybrid Hybrid Hybrid Hybrid Driver x2 Driver x2 Hybrid Hybrid Driver x2 Driver x2 Hybrid Hybrid Hybrid Hybrid

  14. AC7 versus Centillium Maximus w/Intersil)Board Complexity Comparison (48 Port Example) Analog Signal Trace Elimination (PCB, Debug) Advantage TI Centillium Maximus TI AC7 32- Chip Count -27 (Inventory, Manufacturing) Advantage TI Hybrid Hybrid Driver x2 Driver x2 Hybrid Hybrid Driver x2 Driver x2 Hybrid Hybrid Hybrid Hybrid Hybrid Hybrid DSP x16 Codec x12 Driver x2 Driver x2 Hybrid Hybrid DSP x12 Codec x12 Driver x2 Driver x2 Hybrid Hybrid Hybrid Hybrid Hybrid Hybrid Driver x2 Driver x2 Hybrid Hybrid Driver x2 Driver x2 Hybrid Hybrid Hybrid Hybrid Integrated Hybrid (BOM $, Manufacturing) Advantage TI Hybrid Hybrid Driver x2 Driver x2 Hybrid Hybrid Driver x2 Driver x2 Hybrid Hybrid Hybrid Hybrid DSP x12 Codec x12 DSP x12 Codec x12 Hybrid Hybrid Driver x2 Driver x2 Hybrid Hybrid Driver x2 Driver x2 Hybrid Hybrid Hybrid Hybrid Hybrid Hybrid Driver x2 Driver x2 Hybrid Hybrid Driver x2 Driver x2 Hybrid Hybrid Programmable Hybrid (Performance) Advantage TI Hybrid Hybrid Hybrid Hybrid Driver x2 Driver x2 Hybrid Hybrid Driver x2 Driver x2 DSP x16 Codec x12 Hybrid Hybrid DSP x12 Codec x12 Hybrid Hybrid Hybrid Hybrid Driver x2 Driver x2 Hybrid Hybrid Driver x2 Driver x2 Hybrid Hybrid Hybrid Hybrid Hybrid Hybrid Driver x2 Driver x2 Codec Integration (PCB, Inventory) Advantage TI Hybrid Hybrid Driver x2 Driver x2 Hybrid Hybrid Hybrid Hybrid DSP x16 Codec x12 Hybrid Hybrid Driver x2 Driver x2 Hybrid Hybrid Driver x2 Driver x2 Hybrid Hybrid DSP x12 Codec x12 Hybrid Hybrid Hybrid Hybrid Driver x2 Driver x2 Hybrid Hybrid Driver x2 Driver x2 Hybrid Hybrid Hybrid Hybrid Hybrid Hybrid Driver x2 Driver x2 Hybrid Hybrid Driver x2 Driver x2 Hybrid Hybrid Hybrid Hybrid

  15. AC7 versus GSPN G24 (w/Intersil) Board Complexity Comparison (48 Port Example) Hybrid Hybrid Driver x2 Driver x2 Hybrid Hybrid Codec x8 Hybrid Hybrid Driver x2 Driver x2 Hybrid Hybrid Hybrid Hybrid Driver x2 Driver x2 Hybrid Hybrid DSP x16 Codec x8 Hybrid Hybrid Driver x2 Driver x2 Hybrid Hybrid Hybrid Hybrid Codec x8 Driver x2 Driver x2 Hybrid Hybrid Hybrid Hybrid Driver x2 Driver x2 Hybrid Hybrid DSP x16 Codec x8 Hybrid Hybrid Driver x2 Driver x2 Hybrid Hybrid Hybrid Hybrid Driver x2 Driver x2 Hybrid Hybrid Codec x8 Hybrid Hybrid Driver x2 Driver x2 DSP x16 Hybrid Hybrid Hybrid Hybrid Driver x2 Driver x2 Codec x8 Hybrid Hybrid Hybrid Hybrid Driver x2 Driver x2 Analog Signal Trace Elimination (PCB, Debug) Advantage TI Hybrid Hybrid Hybrid Hybrid Driver x2 Driver x2 Hybrid Hybrid Globespan G24 TI AC7 36- Chip Count -27 (Inventory, Manufacturing) Advantage TI Hybrid Driver x2 Hybrid Driver x2 Hybrid Hybrid Codec x8 SRAM Hybrid Driver x2 Hybrid Driver x2 Integrated Hybrid (BOM $, Manufacturing) Advantage TI Hybrid Hybrid SRAM Hybrid Driver x2 Hybrid DSP X24 (MCM) Driver x2 Hybrid Hybrid Codec x8 Hybrid Driver x2 Hybrid Driver x2 Hybrid Hybrid Programmable Hybrid (Performance) Advantage TI SRAM Codec x8 Hybrid Driver x2 Hybrid Driver x2 Hybrid Hybrid SRAM Hybrid Driver x2 Hybrid Driver x2 Hybrid Hybrid Codec x8 YES MCM NO (Board Reliability) Advantage TI Hybrid Driver x2 Hybrid Driver x2 Hybrid Hybrid Hybrid Driver x2 Hybrid Driver x2 DSP X24 (MCM) Hybrid Hybrid Codec x8 Hybrid Driver x2 Hybrid Driver x2 Codec Integration (PCB, Inventory) Advantage TI Hybrid Hybrid Hybrid Driver x2 Hybrid Codec x8 Driver x2 Hybrid SRAM Hybrid Hybrid Driver x2 Hybrid Driver x2 SRAM SRAM Hybrid Hybrid Hybrid Driver x2 SRAM Hybrid Driver x2 Hybrid Hybrid

  16. AC7 versus InfineonBoard Complexity Comparison (48 Port Example) Analog Signal Trace Elimination (PCB, Debug) Advantage TI Infineon TI AC7 42- Chip Count -27 (Inventory, Manufacturing) Advantage TI Hybrid Driver x2 Codec x4 Hybrid Hybrid Hybrid DSP X8 Driver x2 Driver x2 Driver x2 Codec x4 DSP X8 Hybrid Hybrid Hybrid Hybrid Hybrid Driver x2 Codec x4 Hybrid Hybrid Hybrid Driver x2 Driver x2 Driver x2 Codec x4 Hybrid Hybrid Hybrid Hybrid Hybrid Driver x2 DSP X8 Codec x4 Hybrid Hybrid Hybrid Driver x2 Driver x2 Driver x2 Codec x4 Hybrid Hybrid Hybrid Hybrid Integrated Hybrid (BOM $, Manufacturing) Advantage TI DSP x16 Codec x4 Codec x4 Hybrid Driver x2 Hybrid Hybrid Hybrid Driver x2 Driver x2 Driver x2 Hybrid Hybrid Hybrid Hybrid Codec x4 DSP X8 Codec x4 Hybrid Driver x2 Hybrid Hybrid Hybrid Driver x2 Driver x2 Driver x2 DSP X8 Hybrid Hybrid Hybrid Hybrid Codec x4 Codec x4 Hybrid Driver x2 Hybrid Hybrid Hybrid Driver x2 Driver x2 Driver x2 Programmable Hybrid (Performance) Advantage TI Hybrid Hybrid Hybrid Hybrid DSP X8 Codec x4 Codec x4 Hybrid Driver x2 Hybrid Hybrid Hybrid Driver x2 Driver x2 Driver x2 DSP x16 Hybrid Hybrid Hybrid Hybrid Codec x4 Codec x4 Hybrid Driver x2 Hybrid Hybrid Hybrid Driver x2 Driver x2 Driver x2 Hybrid Hybrid Hybrid Hybrid DSP X8 Codec x4 DSP x16 Codec x4 Hybrid Codec Integration (PCB, Inventory) Advantage TI Driver x2 Hybrid Hybrid Hybrid Driver x2 Driver x2 Driver x2 Hybrid Hybrid Hybrid Hybrid Codec x4 Codec x4 Hybrid Driver x2 Hybrid Hybrid Hybrid Driver x2 Driver x2 Driver x2 Hybrid Hybrid Hybrid Hybrid DSP X8 DSP X8 Codec x4 Codec x4 Hybrid Driver x2 Hybrid Hybrid Hybrid Driver x2 Driver x2 Driver x2 Hybrid Hybrid Hybrid Hybrid Codec x4 Codec x4 Hybrid Driver x2 Hybrid Hybrid Hybrid Driver x2 Driver x2 Driver x2 Hybrid Hybrid Hybrid Hybrid

  17. World’s Best End to End Solution”AC7 and AR7” x2 x2 x2 x2 x2 x2 x2 x2 x2 x2 x2 x2 x2 x2 x2 x2 x2 x2 x2 x2 x2 x2 x2 x2 AR7 Single-Chip DSL Router ATM Cells Packets Central Office Local Loop Services Flexible CPE Services & I/F’s PCI VLYNQ TI Power Supply Legacy ADSL Video ADSL2 Data AC7 x16 VoIP READSL Security ADSL2+ Annex I,J 802.11a/b/g ATM orMulti-ProtocolAggregation USB AC7 x16 10/100 DELT • Most Integrated CO Chipset • World’s Most Integrated CPE Chipset • Highly Flexible CO and CPE Service Offerings • LVDS Port Enables Low Cost Aggregation AC7 x16 • End to End ATM or Ethernet Operation • Complete Reference Designs 48 Port Linecard • Most Interoperable Solutions

  18. AC7: System Cost ReductionsToday’s Signal Trace Topology I/F #1: Digital I/F #2: Digital I/F #3: Analog 8 Port Codec Dual Driver Utopia 2 8 Port Xcvr Description Data Dual Driver Three Signal Interfaces #1 Digital – Parallel #2 Digital – Serial #3 Analog – Differential Dual Driver Mgmt Dual Driver Issues Clock/ Control Traces Analog Traces • Too Many Traces • Complex Routing • Higher PCB Costs • Analog Traces susceptible to noise • Parallel interfaces increase FPGA/ASIC costs Utopia 2 Dual Driver 8 Port Xcvr 8 Port Codec Data Dual Driver Dual Driver Mgmt Dual Driver Clock/ Control Traces

  19. AC7: 10x Reduction in Trace Count“Signal Serialization & Analog Signal Trace Elimination” 16 Port Multi- Service Xcvr x2 x2 x2 LVDS Serial I/F 622Mbps x2 x2 Benefit • No Analog Signal Traces • Decreases Routing Density • (Less Traces/Unit Area) • Lowers PCB costs • Simplifies board layout • Reduces ASIC/FPGA pin count x2 x2 x2 I/F #1: Serial I/F #2: Serial Feature Two Signal Interfaces #1 Digital – Serial #2 Digital – Serial #3 Analog – Internal Option to completely serialize all signal traces

  20. AC7: Total Cost of Ownership ImpactTotal Lifetime Component Count Analysis:- AC7 has almost 50M fewer parts than typical competitor- Improves board level and overall product reliability probability - Reduces service and maintenance call probability- Reduces manufacturing complexity

  21. AC7: Total Cost of Ownership ImpactCumulative Lifetime Chipset Assembly Costs Conclusions:- Yields a savings of ~$0.50/port for all scenarios

  22. AC7: Total Cost of Ownership ImpactFewer Devices to Order, Inventory, & Manage Assumptions:- 3,000,000 port product lifetime

  23. AC7: Impacting Operator’s OPEX budgetsNetwork Level Electricity Savings Assumptions:- 3,000,000 port network, All modems active 24 hours/day, 365 days/year, full power, $0.10 kWh- Scenario #1: 1.1W versus 0.85W (AC7), - Scenario #2: 2.5W versus 0.85W (AC7)

  24. Building on the Success of ADSLAdd New Services with Legacy CPE Protection Legacy CPE Interoperability Maintained 50M Chipset Phase I: 1. G.lite Only 35M 30M Legacy CPE Interoperability Maintained Chipset Phase II: 1. G.dmt/G.lite 2. Legacy Interoperable w/CPEs in the field 25M 24Mbps Downstream 20M IV CPE Interoperability Maintained 15M Chipset Phase III: 1. ADSL2, ADSL2+, READSL 2. Scalable up to 24Mbps down 3. Scalable up to 3.8Mbps up 4. Increased reach 5. Legacy Interoperable w/CPEs in the field III 10M 8Mbps 5M Extended Reach Area II 1.5Mbps I Chipset Phase IV: 1. VDSL/ADSL 2. Scalable up to 50+Mbps down 3. Scalable up to 20+Mbps up 2. Legacy Interoperable w/CPEs in the field 896kbps 896kbps 2M 3.8Mbps 4M Upstream 20M

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