Test Bench for Serdes Radiation Qualification

1. Test Bench for Serdes Radiation Qualification A. Aloisio, R. Giordano aloisio@na.infn.it, rgiordano@na.infn.it University of Naples ‘Federico II’ and INFN XII SuperB Workshop - LAPP, Annecy - Mar. 18th, 2010

2. Overview • On-detector SerDes in the ETD framework • Test boards for Rad Tests • The full test bench • Status and work plan • Budget issues • Conclusions XII SuperB Workshop - LAPP, Annecy - Mar. 18th, 2010 2

3. SerDes in rad enviroments Layout by D. Breton LNF, Dec.09 • FCTS links: • Timing & Clock • Commands & Controls • config data • DATA links: • Read-out payload • DS92lv18: • Fixed latency • 1.2 Gbit/s • FCTS and DATA • TLK2711A • Variable latency • Up to 2.7 Gbit/s • DATA only FCTS link Tight latency requirements DS92lv18 Data link No tight latency requirements DS92lv18 or TLK2711A XII SuperB Workshop - LAPP, Annecy - Mar. 18th, 2010

4. DS92LV18 Test board Diff. impedance 120 W • High speed I/O and clocks on SMA connectors with controlled impedance • RX, TX, Controls busses on parallel connectors with matched length and controlled impedance • Static control programming enabled via jumpers • Separate supplies for analog, digital, PLL with sense (4-wire scheme) • Current sensing on each supply • 10 layer PCB, separate power and ground planes TX clk TX out RX in Reference clk Recovered Clock 57 W XII SuperB Workshop - LAPP, Annecy - Mar. 18th, 2010

5. TLK2711A Test Board TX clk TX out RX in • Same logical and physical layout as DS92LV18 board • RX, TX, Controls busses on parallel connectors with pinout as similar as possible to DS, yet quite different • Separate supplies only for generic analog and digital sections (no PLL supply specified) Recovered Clock SERDES Controls Current sense & Test points XII SuperB Workshop - LAPP, Annecy - Mar. 18th, 2010

6. Tektronix DTG5334 18 2 8 18 Controls RX Data out Test Bench (DS92LV18) XILINX ML505 Tektronix MSO70000 Clock Generator FPGA Clk RX Reference Clk Recovered Clk TX Clk Jitter Analyzer TX Data in Power Analyzer Controls AGILENT E5052B RX Serdes TX Serdes 3.3V Power AGILENT N6705A XII SuperB Workshop - LAPP, Annecy - Mar. 18th, 2010

7. Errors and Loss-of-Service presented at SLAC, Oct.09 • Errors in the DS payload can be counted by a BER Tester • Corruption of start/stop bits trigger a Loss-of-Service, LOCK needs to be monitored • FEC coding can moderate error rate, NOT Loss-of-Service XII SuperB Workshop - LAPP, Annecy - Mar. 18th, 2010

8. Clock output XILINX ML505 Virtex5 – XC5VLX50T Clock input GTPdiff. I/O FPGA setup • Testing the SerDes RX section • Drives the SerDes receiver input with serial stream, emulating the DS92LV18 protocol • Receives DS92LV18 parallel output • Cross check received data vs. transmitted • Measure BER and loss-of-service • Testing the SerDesTX section • Drives the SerDes transmitter input with parallel data • Receives the SerDes serial stream, emulating the DS92LV18 protocol • Cross check received data vs. transmitted • Measure BER and loss-of-service • Controls section • Programs and checks controls bits • Console • Status and errors are flagged on a console via JTAG-over-USB and/or Ethernet handled by an embedded micro • TX and RX sections of the SerDes are tested independently and simultaneosly XII SuperB Workshop - LAPP, Annecy - Mar. 18th, 2010

9. TLK vs. DS presented at LNF, Dec.09 • TLK2711A and DS92LV18 test boards are very similar … • …however, chip-sets have different clock frequency, coding scheme, lock procedure and control handling • FPGA firmware will be quite different XII SuperB Workshop - LAPP, Annecy - Mar. 18th, 2010

10. Status and road-map • PCBs have been designed in Nov./Dec. 09, received last week, assembled (1 board per type) and successfully tested • 10 boards per SerDes will be used for rad tests (TID and SEU/SEL) • FPGA firmware for DS testing is presently being developed, firmware for TLK will follow later • Test bench ready in the lab, will be validated as soon as firmware will be available (2 months) • LNS (Catania, Italy) call for proton beam allocation still on hold, expected around summer XII SuperB Workshop - LAPP, Annecy - Mar. 18th, 2010 10

11. Budget Issues • Funding from INFN CSN I: • 1 k€ • Bills till now: • 10+10 PCBs: 2040 € + VAT • Components for 20 boards: 4800 € + VAT (including SMA cables, connectors, …) • We have got a loan from other groups, but we have to pay it down soon XII SuperB Workshop - LAPP, Annecy - Mar. 18th, 2010

12. Conclusions • Boards for TLK and DS evaluation have been developed and tested • Test bench for Rad tests is presently under developments: power consumption, BER, Loss-of-Service • waiting for beam time at LNS (at no cost) Q3/Q4 2010 XII SuperB Workshop - LAPP, Annecy - Mar. 18th, 2010