FE-I4 Digital Test Bench

1. FE-I4 Digital Test Bench Tomasz Hemperek

2. Introduction • SystemVerilog • OVM Methodology • Can to use rtl, syntchesis, post route/layout models 2

3. FE-I4 Top View ANALOG ARRAY (digital part) DIGITAL ARRAY END OF COLUMN END OF CHIP COMMAND DECODER PLL PLL REGISTER MEMORY DATA OUTPUT - verilog model - Implementation (rtl/gate)

4. Chip Interface overview 4

5. OVM OVC (Open Verification Component) Sequences Transaction Example Sequence of Transaction: - send reset - write register 10 - send trigger

6. Slow control transaction • Transaction is an abstract (human readable) information that will be translated (by driver) to correct signal sequence File: /digital/FEI4_A\/TB/cmd/sv/cmd_transfer.sv

7. Slow control sequence • Sequence define transaction sequence. It is possible to run one sequence inside another one. File: digital/FEI4_A/TB/cmd/sv/cmd_master_seq_lib.sv

8. Verification environment (test) • Verification environment connect all interfaces (OVC) blocks. For FE-I4 we heve 4 OVC: - PIX - CMD - REVEIVE - MANUAL

9. Virtual sequence Virtual Sequence defines top sequence of sequences. Sequences can be from different interfaces! Can be started in parallel or one after another.

10. Scoreboard SCOREBOARD: CHECK ! FE-I4 COMMANDS RECEIVED DATA PIXEL HITS

11. Test TEST TOP SEQUENCER SEQ A SEQ B SEQ D SEQ E SEQ C SCOREBOARD

12. Example test TEST : clear_sr SEQUENCER: clear_sr_top_seq configure_seq reset_seq clear_sr_seq read_sr_seq SCOREBOARD : clear_sr_scoreboard

13. Example result

14. Status • All blocks are instantiated and connected (need some polishing and sync with main integration) • Few test are written and are working but needs much more • Need to define manual interface

15. BACKUP SLIDES

16. Slow control transaction • Transaction is an abstract (human readable) information that will be translated (by driver) to correct signal sequence File: /digital/FEI4_A\/TB/cmd/sv/cmd_transfer.sv

17. Slow control sequence • Sequence define transaction sequence. It is possible to run one sequence inside another one. File: digital/FEI4_A/TB/cmd/sv/cmd_master_seq_lib.sv

18. Virtual sequence Virtual Sequence defines top sequence of sequences. Sequences can be from different interfaces! Can be started in parallel or one after another. File: digital/FEI4_A/TB/top_tb/sv/top_seq_lib.sv

19. Receive transaction File: digital/FEI4_A/TB/receive/sv/receive_transfer.sv

20. Example scoreboard Scoreboard receives information from monitors (inputs, outputs). Gathered data can be checked for correctness. File: digital/FEI4_A/TB/top_tb/sv/cmd_scoreboard_lib.sv

21. Test Definition Test organize everything together. You have multiple tests to test different functions. File: digital/FEI4_A/TB/top_tb/tests/top_test_lib.sv

22. Example result

23. How to add test • Create sequences • Create a scoreboard • Create a test • Run simulation How to run simulation: - see vsim_top procedure in digital/FEI4_A/TB/vsim.tcl - change the parameter OVM_TESTNAME to your test class name “vsim +OVM_TESTNAME=test_example_top -novopttop_tb_top”