Transition Delay Fault Testing of Microprocessors by Spectral Method

1. Transition Delay Fault Testing of Microprocessors by Spectral Method Nitin Yogi and Vishwani D. Agrawal Auburn University Department of ECE Auburn, AL 36849, USA 39th Southeastern Symposium on System Theory

2. Outline • Introduction • Defects and transition delay fault model • Microprocessor testing Issues • Problem and Approach • Register-transfer level modeling of transition delay faults • Spectral analysis and test generation • Design for Testability • Experimental Results • Conclusion 39th Southeastern Symposium on System Theory

3. An Open Circuit Defect Reference: W. Maly, “Realistic Fault Modeling for VLSI Testing”, Proceedings of the 24th ACM/IEEE Design Automation Conference, 1987, Miami Beach, Florida, Pages 173-180. 39th Southeastern Symposium on System Theory

4. A Bridging Defect Reference: W. Maly, “Realistic Fault Modeling for VLSI Testing”, Proceedings of the 24th ACM/IEEE Design Automation Conference, 1987, Miami Beach, Florida, Pages 173-180. 39th Southeastern Symposium on System Theory

5. A Possible Delay Defect Reference: W. Maly, “Realistic Fault Modeling for VLSI Testing”, Proceedings of the 24th ACM/IEEE Design Automation Conference, 1987, Miami Beach, Florida, Pages 173-180. 39th Southeastern Symposium on System Theory

6. Stuck-at Fault Model Fault activated Stuck-at 0 A Fault detected B Y C 39th Southeastern Symposium on System Theory

7. Transition (Delay) Fault Model Fault activated Slow-to-rise fault A Fault detected B Y C 39th Southeastern Symposium on System Theory

8. Microprocessor Testing Issues Issues arising from Increased Design Complexity • Increased Demands on Testing • A Viable Test Method: Functional at-speed tests • Advantages: easy to derive; cover many defects • Disadvantages: Long test sequences; full coverage not guaranteed • Need Fault-Oriented Test Generation Methods • Test pattern generators work at gate level • Have very high complexity • RTL Test Generation • Advantages: • Low testing complexity • Early detection of testability issues 39th Southeastern Symposium on System Theory

9. Problem and Approach • The problem is … • Develop an RTL ATPG method to generate functional at-speed tests. • And our approach is … • Circuit characterization using RTL: • RTL test generation • Analysis of information content and noise in RTL vectors. • Test generation for gate-level implementation: • Generation of spectral vectors • Fault simulation and vector compaction 39th Southeastern Symposium on System Theory

10. Faults Modeled at Register-Transfer Level CombinationalLogic Inputs Outputs RTL modules RTL transition delay fault sites FF FF A circuit is an interconnect of several RTL modules. 39th Southeastern Symposium on System Theory

11. Analyzing Bit-Streams of RTL Tests Input 1 Input 2 . . . Vector 1 Vector 2 . . . Bit-stream 0 to -1 Bit-stream of Input 2 39th Southeastern Symposium on System Theory

12. Spectral Characterization of a Bit-Stream Bit stream to analyze Correlating with Walsh functions by multiplying with Hadamard matrix. Bit stream Spectral coeffs. Essential component (others regarded noise) Hadamard Matrix H(3) 39th Southeastern Symposium on System Theory

13. Generation of New Bit-Streams Perturbation Spectral components Generation of new bit-stream by multiplying with Hadamard matrix Essential component retained; noise components randomly perturbed Sign function New bit stream -1 to 0 Bits changed 39th Southeastern Symposium on System Theory

14. PARWAN Processor Reference: Z. Navabi, Analysis and Modeling of Digital Systems. New York: McGraw-Hill, 1993. 39th Southeastern Symposium on System Theory

15. Power Spectrum for “Interrupt” Bit-Stream Analysis of 128 test vectors. Essential components Some noise components Normalized Power Randomlevel(1/128) Spectral Coefficients 39th Southeastern Symposium on System Theory

16. Power Spectrum for “DataIn[5]” Signal Analysis of 128 test vectors. Some essential components Some noise components Normalized Power Theoretical random noiselevel(1/128) Spectral Coefficients 39th Southeastern Symposium on System Theory

17. RTL Design for Testability (DFT) • Goals of DFT: • Improve fault coverage • Most hard-to-detect transition faults were experimentally found to have poor observability • XOR tree as DFT • Low area overhead • Low performance penalty • Hard-to-detect RTL faults used for observation test points • 24 observation test points selected XOR tree To test output Hard-to-detect RTL transition faults 39th Southeastern Symposium on System Theory

18. Experimental Results RTL transition fault characterization PARWAN processor 39th Southeastern Symposium on System Theory

19. Experimental Results * Sun Ultra 5, 256MB RAM ** N. Yogi and V. D. Agrawal, “Spectral RTL Test Generation for Microprocessors,” in Proc. 20th International Conf. VLSI Design, Jan. 2007, pp. 473-478. 39th Southeastern Symposium on System Theory

20. Experimental Results Stuck-at Vectors 39th Southeastern Symposium on System Theory

21. Experimental Results 39th Southeastern Symposium on System Theory

22. Conclusion • Spectral RTL ATPG technique applied to PARWAN processor for transition delay faults. • Proposed ATPG method provides: • Good quality “almost” functional at-speed transition delay tests • Lower test generation complexity • Enables testability appraisal at RTL • RTL based XOR tree as DFT improved fault coverage. • Test optimization for multiple fault models: • Yogi and Agrawal, “Optimizing Tests for Multiple Fault Models,” submitted to the North Atlantic Test Workshop 2007. 39th Southeastern Symposium on System Theory

23. Thank You ! Questions ? 39th Southeastern Symposium on System Theory