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MODERN 2010 Review ENIAC-120003 MODERN Ref. Technical Annex MODERN_PartB Rev2 v3.3

MODERN 2010 Review ENIAC-120003 MODERN Ref. Technical Annex MODERN_PartB Rev2 v3.3. WP1: Giuliana Gangemi WP2: Andr é Juge WP3: Wilmar Heuvelman WP4: Davide Pandini WP5: Loris Vendrame Coordinator: Jan van Gerwen Date: March 1 st , 2010 ( 09.00 - 15.00 hrs)

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MODERN 2010 Review ENIAC-120003 MODERN Ref. Technical Annex MODERN_PartB Rev2 v3.3

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  1. MODERN 2010 Review ENIAC-120003 MODERNRef. Technical Annex MODERN_PartB Rev2 v3.3 WP1: Giuliana Gangemi WP2: André Juge WP3: Wilmar Heuvelman WP4: Davide Pandini WP5: Loris Vendrame Coordinator: Jan van Gerwen Date: March 1st, 2010 (09.00 - 15.00 hrs) Review period: m13 : m22 (2010-12-31)

  2. Agenda (1) • General information (Jan) • Objectives • Consortium • Relationship between workpackages • Gantt Chart • Resources planned and used • Overview of deliverables and milestones status • Cooperation, dissemination and exploitation • Project management: progress, funding problems and amendments • Other issues, Q&A • For WP1 (Giuliana), WP2 (André), WP3 (Wilmar) and WP4 (Davide) • Relationship between workpackages • Progress, highlights and lowlights • Matrices showing ‘Domain and Technology Overview per Task and Partner’ • Link withother WPs and Tasks • Technical status and achievements of deliverables (incl. changes) • Cooperation • Dissemination (publications, patents), exploitation • Other issues, Q&A MODERN 2010 Review March 1st, 2011

  3. Agenda (2) • For WP5 (Loris) • Relationship between workpackages • Progress, highlights and lowlights • Technical status and achievements of deliverables (incl. changes) • Structuring of demonstrators: goals and objectives • Link withother WPs and Tasks • Cooperation • Dissemination (publications, patents), exploitation • Other issues, Q&A MODERN 2010 Review March 1st, 2011

  4. Specifically, the main goals of the project are: • Advanced, yet accurate, models of process variations for nanometre devices, circuits and complex architectures. • Effective methods for evaluating the impact of process variations on manufacturability, design reliability and circuit performance. • Reliability, noise, EMC/EMI. • Timing, power and yield. • Design methods and tools to mitigate or tolerate the effects of process variations on those quantities applicable at the device, circuit and architectural levels. • Validation of the modelling and design methods and tools on a variety of silicon demonstrators. Layout and strain induced variability (Synopsys) Objectives • The objective of the MODERN project is to develop new paradigms in integrated circuit design that will enable the manufacturing of reliable, low cost, low EMI, high-yield complex products using unreliable and variable devices. MODERN 2010 Review March 1st, 2011

  5. Consortium • The MODERN Consortium features strong competence and expertise in the field of advanced technologies, with a well-balanced participation between Large Industries, SMEs, Research Centres and Universities from all over Europe. MODERN 2010 Review March 1st, 2011

  6. Relationship between workpackages MODERN 2010 Review March 1st, 2011

  7. Gantt Chart (1) MODERN 2010 Review March 1st, 2011

  8. Gantt Chart (2) MODERN 2010 Review March 1st, 2011

  9. Resources planned and used MODERN 2010 Review March 1st, 2011

  10. Overview of deliverables and milestones status (1)Deliverables MODERN 2010 Review March 1st, 2011

  11. Overview of deliverables and milestones status (2)Milestones MODERN 2010 Review March 1st, 2011

  12. Website Public section Restricted section MODERN 2010 Review March 1st, 2011

  13. Cooperation, dissemination and exploitation • A Workshop at DATE 2010 with the theme ‘The Fruits of Variability Research in Europe’ was organized. This workshop was a co-operation of the UK EPSRC project, FP7 STREP project REALITY and MODERN • VARI Workshop, 2010 May 26-27, Montpellier, France • Contribution to the Workshop on Simulation and Characterisation of Statistical CMOS Variability and Reliabilitywas presented, Sept. 9th 2010, Bologna, Italy • MODERN participated in the Poster & Demo Session at European Nanoelectronics Forum 2010 in Madrid, Spain • Large number of publications • Main meetings: • General meetings in Catania (Nov. 9&10, 2010) attended by 30+ persons present and 10+ called in • Due to the travel restrictions that many companies/institutes still face most of the interaction between partners is by phone and email MODERN 2010 Review March 1st, 2011

  14. Project management: progress, funding problems and amendments • Progress: All planned deliverables ready • Most uncertainties in countries causing funding and (national) administrative issuese.g. Italy, Swiss, Spain and Austria, are resolved • Amendments: • The change of project coordinator from ST to NXP and ST-Crolles being replaced by ST-Grenoble • The removal of some inconsistencies between some deliverables • The subcontracting of work by Glasgow to GSS Ltd. • CSEM withdraws due to lack of national funding as of 29-06-2010 • To account for the leaving of some NXP employees and a related change in direction of the NXP PDM group the deliverables D5.3.2 and D5.3.3 are (slightly) changed • To account for some technical difficulties encountered in the research activities within ST-I Tasks 3.1, 3.4 and 5.3 are (slightly) changed MODERN 2010 Review March 1st, 2011

  15. Other issues Q&A MODERN 2010 Review March 1st, 2011

  16. Example (Davide)WP4 Domain Overview per Task and Partner MODERN 2010 Review March 1st, 2011

  17. Examples (Andre, Davide)Technology Overview per Task and Partner MODERN 2010 Review March 1st, 2011

  18. Example (Davide)WP4: Link with other WPs and Tasks WP5 WP3 WP4 UPC, LETI UPC, LETI T5.2 T3.3 T4.1 ST I LETI, TMPO T5.3 T4.2 T3.4 THL T4.3 UPC, TMPO, ST I ST I T4.4 THL, LIRM T4.5 MODERN 2010 Review March 1st, 2011

  19. WP1 agenda • Progress, highlights and lowlights • Matrices showing ‘Domain and Technology Overview per Task and Partner’ • Link withother WPs and Tasks • Technical status and achievements of deliverable D1.3 • Cooperation • Dissemination (publications, patents), exploitation • Other issues, Q&A MODERN 2010 Review March 1st, 2011

  20. Outline • Introduction • Progress, highlights and lowlights • Matrices showing‘Domain and Technology Overview per Task and Partner’ D1.3 • Link with other WPs and Tasks • Cooperation • Other issues, Q&A MODERN 2010 Review March 1st, 2011

  21. Introduction: Progress, highlights and lowlights PERIOD UNDER REVIEW 1. Clearly define the issues related to nano-electronic technologies that will be tackled in the MODERN project (e.g.,sensitivity of performances, power, yield, deficiencies of existing design techniques, etc). 2. Set the target technologies for which the above listed problems will be faced. 3. Define the specifications of the prototype tools, methods and flows that will come up as solutions of the previously listed problems. 4. Define the requirements of the integration work needed to embed the new tools into the existing design frameworks provided by the EDA partners within the flows in use at ST, NMX, IFX,THL, AMS and NXP. 5. Define up front all activities of all WPs of MODERN exception made of the management. HIGHLIGHT : Activities recovered past delay D1.3 released OCT 2010 M1.1Problem definition and Tests M1.4 user guides M1.2 Integraton specs MODERN 2010 Review March 1st, 2011

  22. Matrices showing‘Domain and Technology Overview per Task and Partner’ D1.3 MODERN 2010 Review March 1st, 2011

  23. Matrices showing‘Domain and Technology Overview per Task and Partner’ D1.3 MODERN 2010 Review March 1st, 2011

  24. Matrices showing‘Domain and Technology Overview per Task and Partner’ D1.3 MODERN 2010 Review March 1st, 2011

  25. Matrices showing‘Domain and Technology Overview per Task and Partner’ D1.3 MODERN 2010 Review March 1st, 2011

  26. Matrices showing‘Domain and Technology Overview per Task and Partner’ D1.3 MODERN 2010 Review March 1st, 2011

  27. Link with other WPs and Tasks MODERN 2010 Review March 1st, 2011

  28. Collaborations WP leader: ST-I Strong dependence on partners: NMX, NXP,THL,IFX,AMS,ST-I, ST-F Collaboration with partners: NMX, NXP,THL,IFX,AMS,ST-I,SNPS ,ST-F, Telephone conferences with: NMX,NXP,THL,IFX,AMS,ST-I,SNPS ,ST-F according requirements of deliverables ALL SEPT – OCT 2010. With WP Leaders weekly since the month of December. MODERN 2010 Review March 1st, 2011

  29. WP2 agenda • Progress, highlights and lowlights • Matrices showing‘Domain and Technology Overview per Task and Partner’ • Link withother WPs and Tasks • Technical status and achievements of deliverables (incl. changes): D2.1.1, D2.2.3, D2.3.2 and D2.5.1 • Cooperation • Dissemination (publications, patents), exploitation • Other issues, Q&A MODERN 2010 Review March 1st, 2011

  30. WP3 agenda Progress, highlights and lowlights Matrices showing‘Domain and Technology Overview per Task and Partner’ Link withotherWPs and Tasks Cooperation Dissemination (publications, patents), exploitation Other issues, Q&A MODERN 2010 Review March 1st, 2011

  31. WP3Progress, highlights and lowlights • All deliverables for 2010 delivered as planned (M12) • Deliverables M24 are on schedule • Highlights: • Very successful meeting with WP3 partners on Nov. 2010 in Catania • VARI 2010 conference organized by LIRMM • Lowlights • Withdrawal of partner CSEM due to Swiss funding issues • Funding of Italian partners delayed MODERN 2010 Review March 1st, 2011

  32. MatrixApplication overview per task and partner MODERN 2010 Review March 1st, 2011

  33. WP3 Domain Overview per Task and Partner (tbd) MODERN 2010 Review March 1st, 2011

  34. WP3 symbolic synergy T3.1 T3.3 T3.4 T3.2 MODERN 2010 Review March 1st, 2011

  35. WP3: Link with other WPs and Tasks WP2 WP3 WP4 T2.3 T3.1 NXP ST I, UNRM T2.5 NMX NMX T3.2 T3.3 UPC, LETI T4.1 IFX T3.4 T4.2 ST I WP5 T5.1 T5.2 T5.3 MODERN 2010 Review March 1st, 2011

  36. T3.1: surrogate behavioral models • The optimization procedures considered inT3.2 requires the availability of a circuit simulator (e.g. SPICE). Each simulation run may require a large computing time; • GOAL in T3.2: development of surrogate models for the circuit behaviour based on learning machines (e.g. Neural Networks, Support Vector Machines); • So as to employ the surrogate model instead of the circuit simulator. Red: Surrogate model outputs Blue: Original outputs • A larger experimentation of surrogate models is in order; • New input-output data sets for different circuits are expected from ST-I; • Results of main interest for task T3.2; • Cooperation between UNRM and ST-I essential. Output START_PH1: Comparison on the test set Good performance of surrogate models on the test set MODERN 2010 Review March 1st, 2011 36

  37. T3.2: Analysis of Analogue Sensing Memory Circuit with RandomSpice Sense Amplifier circuit of NMX analyzed with RandomSpice (UNGL) SPICE frontend for advanced statistical circuit simulation. Allows use of UNGL-developed PCA and non-linear power method compact model parameter generation methods. Statistical enhancement of circuit simulation to access very rare circuit instances. Database and post-processing backend for power/performance/yield predictions. MODERN 2010 Review March 1st, 2011

  38. T3.3: M&C Strategies for AMS & RF ADC search algorithm incl. redundancy • Switches • Monitor concepts: ring oscillator, current sensing • Control: “frequency locked loop”, analog control loop • Aging induced offsets • Avoid offset generation: e.g. chopping (comparator) • Correction of static & dynamic effects: e.g. error correction by redundancy • Burn-in: dedicated stress to increase robustness and compensate PV MODERN 2010 Review March 1st, 2011 38

  39. T3.4: Neptune 5 test chip specs Current floor plan proposal Spectrum of the output of FM buffer with and without digital noise present in the system Links to WP5, demonstrator test-chip on substrate noise MODERN 2010 Review March 1st, 2011

  40. WP3Cooperation tbd MODERN 2010 Review March 1st, 2011

  41. WP3Dissemination tbd MODERN 2010 Review March 1st, 2011

  42. WP4: Outline Progress, highlights and lowlights Matrices showing‘Domain and Technology Overview per Task and Partner’ Link withother WPs and Tasks, Cooperations Dissemination (publications, patents), exploitation Other issues, Q&A MODERN 2010 Review March 1st, 2011

  43. WP4 Task Structure T4.1: Variability-aware design (LETI, UPC) T4.2: Variation-tolerant, robust, low-noise and low-EMI architectures/micro-architectures (ELX,TMPO, LETI, POLI, ST I, TEKL) T4.3: Design of reliable systems (ISD, THL, NMX, ST F) T4.4: Design of regular architectures and circuits for high manufacturability and yield (ST I, TMPO, UPC, UNBO) T4.5: Distributed reconfigurable PV-robust architectures (THL, LIRM) MODERN 2010 Review March 1st, 2011

  44. WP4 M24 Deliverables MODERN 2010 Review March 1st, 2011

  45. WP4 Domain Overview per Task and Partner MODERN 2010 Review March 1st, 2011

  46. WP4 Technology Overview per Task and Partner MODERN 2010 Review March 1st, 2011 MODERN 2010 Review March 1st, 2011

  47. D4.1.1: PV-aware adaptive compensation techniques (1) • Advantages: • Operate on local, realistic silicon corner (vs wc analysis) • Monitor/adjust to variations along circuit lifetime • Optimize timing / power • LAVS (Local Adaptive Voltage Scaling Architecture) • Monitor / Adapt V,F using • Delay-based Diagnostic system • Adaptation controller • Local Power Manager MODERN 2010 Review March 1st, 2011

  48. D4.1.1: PV-aware adaptive compensation techniques (2) MODERN 2010 Review March 1st, 2011 • Study of Delay-Based Variation Control using Body Bias (BB) and Voltage Scaling (VS) • Variation is Monitored using on-chip sensors: Leakage / Dynamic Power / Delay • Based on sensor information, BB and VS is applied to reduce variability • Study of correlation between observables: • Delay distribution shows larger correlation • Use of delay sensors can reduce not only delay variability, but also leakage and dynamic power variability • Voltage Scaled Elastic clock architecture (with task 4.2) • Elastic clocks allow clock period margin reduction • Objective of analysis is to quantify this reduction with respect to Voltage noise • Study of correlation between voltage at several chip locations.

  49. D4.2.2: PV-tolerant noise and EMI reduction techniques (1) • QDI asynchronous NoC based on Muller gates: fully designed in STM 32nm technology • GALS interfaces to communicate with synchronous IPs: • 2 Macros: Target / Initiator • Performance • Noc Area: 108 µm x 60 µm • Asynchronous Peak :~1GHz @tt32_1.00V_25C • Interfaces :800MHz @tt32_1.00V_25C • Latency :1 router : 0.8 nsinitiator to target : 1.6 ns MODERN 2010 Review March 1st, 2011

  50. D4.2.2: PV-tolerant noise and EMI reduction techniques (2) Smooth design flow integration 28% reduction of IC pad current peaks. 25% reduction of Max Dynamic Voltage Drop. 55% reduction of IC pad voltage fluctuations. Up to 30 dBµV reduction of digital core conducted EMI harmonics Flow is now under formal evaluation by STon 2 different product lines • “Power shaping” methodology and design flow for power robustness and low-EMI • Uses standard indudstry formats (Verilog, SDF SDC), exports modified Verilog + flow specific clock tree synthesis directives. • Proposed methodology applied to a 90nm IC reference design provided by ST-I. MODERN 2010 Review March 1st, 2011

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